AN3100

Configuring SPEAr MPMC for a specific DDR memory part

Doc ID 16606 Rev 2

11/24

4

Configuring SPEAr MPMC for a specific DDR memory

part

Many timing parameters such as CAS latency, Trc, refresh timings etc. need to be fulfilled for

reliable DDR read/writes. These timing parameters become much more important at higher

frequencies like 333 MHz or 666 MT/seconds. You need to configure these timing

parameters in the MPMC registers at system startup before using DDR. Although almost all

DDR manufacturers fulfil the JEDEC specifications, still these timing parameters vary

slightly with different memory manufacturers and also for different memory parts within the

same DDR manufacturer. So you must program the SPEAr MPMC register to configure the

timing parameters based on the memory device and the clock frequency in use on the

application board.

For many MPMC registers, you need to convert the timings mentioned in the memory

datasheet to number of clock cycles according to the required frequency. After the

conversion, these values must be written to the correct bit field location in the right register

address of MPMC: this requires careful study.

To help you, ST provides a Web tool giving the complete MPMC register configuration for

SPEAr devices and for each selected DDR part.

Note:

To access the Web tool for generating the register configuration file, please contact your ST

representative.

You need to provide the following information:

1.

Product name, for example SPEAr600 or SPEAr300

2.

DDR part to be used

3.

Required DDR frequency

4.

CAS latency supported by the selected DDR part at the selected frequency

5.

Required burst length (fixed to 4 in case of DDR2)

The figure below shows a snapshot of the page of the Web tool.

Figure 3.

ST SPEAr600 configuration manager