DDR controller delay lines tuning

AN3100

14/24

Doc ID 16606 Rev 2

memory data path, in contrast to the read parameters dll_dqs_delay_x. These parameters

allow these two clocks to be delayed by a fixed percentage of the core clock.

In short, for writing to DDR you need to:

1.

Align DQS signal with respect to the clock

2.

Adjust DQ signals to the specs (1/4 cycle) relative to DQS.

This can be done by programming the following registers:

●

MPMC_CTL_40: to align DQS (write) to the clock signal

●

MPMC_CTL_41: to adjust DQ signal to within 1/4 clock cycle of DQS.

There is only one register, mentioned previously, to center the read DQS signal in the clock

signal:

MPMC_CTL_39: to activate the DQS signal in the middle of the data valid signal

The delay introduced by these parameters can be determined based on the following

equation,

Delay = delays in one cycle *param [6:0]/128. ----------- (Equation 1)

Where param is one of the following parameters:

●

wr_dqs_shift

●

dqs_out_shift

●

dll_dqs_delay_X

The value “delays in one cycle” is automatically generated by the memory controller DCC

(delay compensation circuit) master delay line that calculates the number of delay elements

that constitute a complete cycle in an adaptive way (according to PVT variations).

5.2.1

Example using these parameters

At DDR frequency of 333 MHz (666 MT/sec):

One cycle time = 3 ns

If Write DQS generated by the memory controller is in phase with the clock on the controller

side and also at the DRAM end (effects of PCB tracks, substrate track length are

compensated), then DQS can be aligned to the clock by two values of wr_dqs_shift

parameter which are 0 or 0x7F.

Equation 1

Delay

= 3 ns x 0 = 0 or

= 3 ns x 128/128 = 3 ns

In both cases either the delay between write DQS and clock is zero or 3 ns (one clock

cycle), so the two signals which are Data strobe/DQS and clock would be aligned.

But in actual scenarios, the write DQS generated by the memory controller is slightly shifted.

At higher frequencies like 333 MHz, clock cycle time is very small (3 ns) and a deviation of

more than ¼ clock cycle time is not accepted. So we need to change this parameter value

from its ideal value of 0x0 or 0x7F. Just for reference, the value for this parameter in the

SPEAr300 evaluation board is 0x7F.