Pad descriptions and configurations

AN3100

18/24

Doc ID 16606 Rev 2

Except for some reference pads, all the pads can be divided into two main groups on the

basis of the nature of the digital cell present in the pad:

●

Data cell (BDPROGDDRSCARUDQP_VDDE_1V8_2V5_SF_TF_2ROWS ,

BDPROGDDRSCARUDQP_GNDE_1V8_2V5_SF_TF_2ROWS )

●

Clock cell (BDCLKRESDDRSCARUDQP_INPUT_DQS_1V8_2V5_SF_TF_2ROWS )

The figures below show the data cell and the clock cell architecture.

Figure 4.

Data cell architecture

GNDEPA D or VDDEPAD

EN

TEN

DDR2V5

ZOUTPROGA2V5

PROGB2V5

ENZI

ZI

PU2V5

PDN2V5

ODTA

ODTEN

ODTB

MODEZI2V5

REFSSTL

On-die terminations

VDDE

IOPAD

300

Ω

300

Ω

300

Ω

300

Ω

VDDE

VDDE

50 k

Ω

50 k

Ω

BOOST TRIGGER A[0:6]SRC

VDD GND

VDDE

GNDE

PROGA2V5

TM

A

TA

Logic

block