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UPD64AMC датащи(PDF) 18 Page - NEC |
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UPD64AMC датащи(HTML) 18 Page - NEC |
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18 / 64 page ![]() 18 µPD64A, 65 Data Sheet U14380EJ2V0DS00 3.4 Control Register 1 (P4) Control register 1 consists of 8 bits. The contents that can be controlled are as shown below. When reset, the register becomes 0010 0110B. Table 3-6. Control Register 1 (P4) Bit b7 b6 b5 b4 b3 b2 b1 b0 Name — — KI S0/S1 S2 S1/LED KI/O S0 Pull-down Pull-down STOP release mode mode mode Set 0 Fixed Fixed OFF OFF Disable S1 IN OFF value 1 to “0” to “0” ON ON Enable LED OUT IN When reset 00100110 b0 : Specifies the input mode of the S0 port. “0” = OFF mode (high impedance); “1” = IN (INPUT mode). b1 : Specifies the I/O mode of the KI/O port. “0” = IN (INPUT mode); “1” = OUT (OUTPUT mode). b2 : Specifies the I/O mode of the S1/LED port. “0” = S1 (INPUT mode); “1” = LED (output mode). b3 : Specified the use of the STOP mode release by S2 port (with/without pull-down resistor). “0” = disable (pull- down unavailable); “1” = enable (pull-down available). b4 : Specifies the availability of the pull-down resistor in S0/S1 port INPUT mode. “0” = OFF (unavailable); “1” = ON (available) b5 : Specifies the availability of the pull-down resistor in KI port. “0” = OFF (unavailable); “1” = ON (available). Remark In OUTPUT mode or in OFF mode, all the pull-down resistors are automatically disconnected. |
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