UPD64AMC datasheet(17/64 Pages) NEC

17 / 64 page

µPD64A, 65

Data Sheet U14380EJ2V0DS00

3.2.4 S2 port (bit 1 of P1)

The S2 port is an input port.

Use of the STOP mode release of the S2 port can be specified by bit 3 of the P4 register.

When using the pin as a key input from a key matrix, enable (bit 3 of P4 register is set to 1) the use of the STOP

mode release (at this time, a pull-down resistor is connected internally.) When the STOP mode release is disabled

(bit 3 of P4 register is set to 0), it can be used as the input port which does not release the STOP mode even if

the release condition is established (at this time, a pull-down resistor is not connected internally.)

The state of the pin can be read in both cases.

At reset, the pin is set to INPUT mode where the STOP mode release is disabled, and goes to high-impedance

state.

3.3 Control Register 0 (P3)

Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.

When reset, the register becomes 0000 0011B.

Table 3-4. Control Register 0 (P3)

Bit

Name

—

DP (Data pointer)

TCTL

CARY

MOD1

MOD0

DP10Note

DP9

DP8

Set

Fixed

1/1

Refer to Table 3-5.

value

to “0”

1/2

OFF

When reset 0

b0, b1 : These bits specify the carrier frequency and duty ratio of the REM output.

: This bit specifies the availability of the carrier of the frequency specified by b0 and b1.

“0” = ON (with carrier); “1” = OFF (without carrier; high level)

: This bit changes the carrier frequency and the timer clock’s frequency division ratio.

“0” = 1/1 (carrier frequency: the specified value of b0 and b1; timer clock: fX/64)

“1” = 1/2 (carrier frequency: half of the specified value of b0 and b1; timer clock: fX/128)

Table 3-5. Timer Clock and Carrier Frequency Setup

Timer Clock

Carrier Frequency (Duty Ratio)

0000fX/64

fX/8 (Duty 1/2)

fX/64 (Duty 1/2)

fX/96 (Duty 1/2)

fX/96 (Duty 1/3)

××

Without carrier (high level)

0000fX/128

fX/16 (Duty 1/2)

fX/128 (Duty 1/2)

fX/192 (Duty 1/2)

fX/192 (Duty 1/3)

××

Without carrier (high level)

b4, b5, b6 : These bits specify the high-order 3 bits (DP8, DP9 and DP10) of ROM’s data pointer.

Note Set DP10 of the

µPD64A to "0".

Remark

×: don’t care

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