AN4504 datasheet(30/41 Pages) STMICROELECTRONICS

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First-in first-out (FIFO) buffer

AN4504

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6.2.3

FIFO source register (0x2F)

This register is updated at every ODR and provides information about the FIFO buffer

status.



WTM bit is set high when FIFO content exceeds watermark level.



OVRN bit is set high when FIFO buffer is full, this means that the FIFO buffer contains

32 unread samples. At the following ODR a new sample set replaces the oldest FIFO

value. The OVRN bit is reset when the first sample set has been read.



EMPTY flag is set high when all FIFO samples have been read and FIFO is empty.



FSS[4:0] field always contains the current number of unread samples stored in the

FIFO buffer. When FIFO is enabled, this value increases at ODR frequency until the

buffer is full, whereas it decreases every time that one sample set is retrieved from

FIFO.

The watermark flag, the FIFO overrun and FIFO empty events can be enabled to generate a

dedicated interrupt on the DRDY/INT2 pin by configuring CTRL_REG3.



I2_WTM bit drives the watermark flag (WTM) on the DRDY/INT2 pin.



I2_OVRN bit drives the overrun event (OVRN) on the DRDY/INT2Y pin.



I2_Empty bit drives the empty event (EMPTY) on the DRDY/INT2 pin

If one or more bits are set to “1”, the DRDY/INT2 pin status is the logical OR combination of

the three signals.

Table 30. FIFO_SRC_REG

WTM

OVRN

EMPTY

FSS4

FSS3

FSS2

FSS1

FSS0

Table 31. FIFO_SRC_REG behavior assuming WTM[4:0] = 15 (hex)

WTM

OVRN

EMPTY

FSS[4:0]

Unread FIFO samples

Timing

00000

00001

t0 + 1/ODR

00010

t0 + 2/ODR

...

01111

t0 + 15/ODR

10000

t0 + 16/ODR

...

11110

t0 + 30/ODR

11111

t0 + 31/ODR

11111

t0 + 32/ODR

Table 32. CTRL_REG3 (0x22)

I2_WTM

I2_ORun

I2_Empty

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