AN4504 datasheet(28/41 Pages) STMICROELECTRONICS

28 / 41 page

First-in first-out (FIFO) buffer

AN4504

28/41

DocID026419 Rev 1

Table 26 represents the FIFO full status when 32 samples are stored in the buffer while

Table 27 represents the next step when the 33rd sample is inserted into FIFO and the 1st

sample is overwritten. The new oldest sample set is made available in the output registers.

When FIFO is enabled and the mode is different from Bypass, the L3G4200D output

registers (28h to 2Dh) always contain the oldest FIFO sample set.

6.2

FIFO registers

The FIFO buffer is managed by three different accelerometer registers, two of these allow

enabling and configuring FIFO behavior, the third provides information about the buffer

status.

6.2.1

Control register 5 (0x24)

The FIFO_EN bit in CTRL_REG5 must be set to 1 in order to enable the internal first-in first-

out buffer; when this bit is set, the gyroscope output registers (28h to 2Dh) don’t contain the

current angular rate value but they always contain the oldest value stored in FIFO.

Table 27. FIFO overrun representation (33rd sample set stored and 1st sample

discarded)

Output

registers

0x28h

0x29h

0x2Ah

0x2Bh

0x2Ch

0x2Dh

Xl(1)

Xh(1)

Yl(1)

Yh(1)

Zl(1)

Zh(1)

FIFO index

Sample set

FIFO(0)

Xl(1)

Xh(1)

Yl(1)

Yh(1)

Zl(1)

Zh(1)

FIFO(1)

Xl(2)

Xh(2)

Yl(2)

Yh(2)

Zl(2)

Zh(2)

FIFO(2)

Xl(3)

Xh(3)

Yl(3)

Yh(3)

Zl(3)

Zh(3)

FIFO(3)

Xl(4)

Xh(4)

Yl(4)

Yh(4)

Zl(4)

Zh(4)

...

FIFO(30)

Xl(31)

Xh(31)

Yl(31)

Yh(31)

Zl(31)

Zh(31)

FIFO(31)

Xl(32)

Xh(32)

Yl(32)

Yh(32)

Zl(32)

Zh(32)

Table 28. FIFO enable bit in CTRL_REG5

FIFO_EN

XXXXX

AN4504 датащи(PDF) 28 Page - STMicroelectronics

AN4504 датащи(HTML) 28 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

датащи скачать

ссылки URL