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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AN4504 датащи(PDF) 29 Page - STMicroelectronics |
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AN4504 датащи(HTML) 29 Page - STMicroelectronics |
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29 / 41 page  DocID026419 Rev 1 29/41 AN4504 First-in first-out (FIFO) buffer 41 Figure 13. FIFO_EN connections block diagram 6.2.2 FIFO control register (0x2E) This register is dedicated to FIFO mode selection and watermark configuration. The FM[2:0] bits are dedicated to defining FIFO buffer behavior: 1. FM[2:0] = (0,0,0): Bypass mode 2. FM[2:0] = (0,0,1): FIFO mode 3. FM[2:0] = (0,1,0): Stream mode 4. FM[2:0] = (0,1,1): Stream-to-FIFO mode 5. FM[2:0] = (1,0,0): Bypass-to-Stream The trigger used to activate the Stream-to-FIFO and Bypass-to-Stream modes is related to the IA bit value of the selected INT1_SRC register and does not depend on the interrupt pin value and polarity. The trigger is generated also if the selected interrupt is not driven to an interrupt pin. The WTM[4:0] bits are intended to define the watermark level; when FIFO content exceeds this value, the WTM bit is set to “1” in the FIFO source register. Table 29. FIFO_CTRL_REG b7 b6 b5 b4 b3 b2 b1 b0 FM2 FM1 FM0 WTM4 WTM3 WTM2 WTM1 WTM0 |
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