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AN2644 датащи(PDF) 30 Page - STMicroelectronics |
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AN2644 датащи(HTML) 30 Page - STMicroelectronics |
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30 / 64 page ![]() The LLC resonant half-bridge converter AN2644 30/64 soft turn-on. They cease to conduct before the transitions of the half-bridge. The operation is DCM, then ZCS occurs by definition. Figure 19. Operation above resonance (f > fR1): main waveforms in DCMAB operation at light load 2.3.3 Operation below resonance (fR2 < f < fR1, R>Rcrit) In this operating mode the converter still exhibits its usual frequency vs. load characteristic. We will consider two submodes where, in a closed-loop regulated system, DCM operation gets deeper and deeper as the output load is increased and frequency is moved away from resonance. DCMAB at medium-light load This "below-resonance" DCM submode is exactly equal to the above-resonance DCMAB submode previously considered. The waveforms are shown in Figure 20 and it is possible to see that they match those shown in Figure 19. Note only that in this case the condition IR = I(Lp) at t=t1 occurs at a considerably higher power level than in the case of the above-resonance DCMAB submode (2:1 in the example shown). DCMB at heavy load This "below-resonance" DCM submode, which is unique to below resonance operation, actually comprises two submodes (DCMB2 & DCMB1) as frequency goes away from resonance. Their waveforms do not differ much, only those of DCMB2 will be shown. It is possible to identify eight fundamentals subintervals and the relevant waveforms are I(D2) = D2 current V(D2) = D2 anode voltage I(Q2) = Q2 current I(Lp) = Lp (magnetizing) current Vc = Resonant capacitor voltage LVG = Q2 gate I(D1) = D1 current V(D1) = D1 anode voltage I(Q1) = Q1 current IR = Tank circuit’s current VHB = Node HB voltage HVG= Q1 gate I(D2) = D2 current V(D2) = D2 anode voltage I(Q2) = Q2 current I(Lp) = Lp (magnetizing) current Vc = Resonant capacitor voltage LVG = Q2 gate I(D1) = D1 current V(D1) = D1 anode voltage I(Q1) = Q1 current IR = Tank circuit’s current VHB = Node HB voltage HVG= Q1 gate t 0 t 0 t 1 t 1 t 3 t 3 t 5 t 5 t 4 t 4 t 2 t 2 Q1 OFF Q2 ON Q1 ON Q2 OFF t 6 t 6 t 8 t 8 t 9 t 9 t 7 t 7 t 10 t 10 Q1 ON Q2 OFF |
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