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ADAV802 датащи(PDF) 30 Page - Analog Devices |
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ADAV802 датащи(HTML) 30 Page - Analog Devices |
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30 / 53 page ![]() ADAV802 Preliminary Technical Data Rev. Pr G | Page 30 of 53 Table 30. Record Port Control Register RES RES CLKSRC1 CLKSRC0 WLEN1 WLEN0 SPMODE1 SPMODE0 7 6 5 4 3 2 1 0 ADDRESS = 0000110 RES Reserved CLKSRC1-0 Selects the Clock Source for generating the OLRCLK and OBCLK 00 = Record Port is a Slave 01 = Recovered PLL Clock 10 = Internal Clock 1 11 = Internal Clock 2 WLEN1-0 Selects the Serial Output Word Length 00 = 24 Bits 01 = 20 Bits 10 = 18 Bits 11 = 16 Bits SPMODE1-0 Selects the serial format of the Record Port 00 = Left Justified 01 = I2S 10 = Reserved 11 = Right Justified Table 31. Auxiliary Output Port Register RES RES CLKSRC1 CLKSRC0 WLEN1 WLEN0 SPMODE1 SPMODE0 7 6 5 4 3 2 1 0 ADDRESS = 0000111 RES Reserved CLKSRC1-0 Selects the Clock Source for generating the OAUXLRCLK and OAUXBCLK 00 = Auxiliary Record Port is a Slave 01 = Recovered PLL Clock 10 = Internal Clock 1 11 = Internal Clock 2 WLEN1-0 Selects the Serial Output Word Length 00 = 24 Bit 01 = 20 Bits 10 = 18 Bits 11 = 16 Bits SPMODE1-0 Selects the serial format of the Auxiliary Record Port 00 = Left Justified 01 = I2S 10 = Reserved 11 = Right Justified |
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