ADAV802_15 datasheet(24/53 Pages) AD

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ADAV802

Preliminary Technical Data

Rev. Pr G | Page 24 of 53

Table 23. Transmitter User Bit Buffer Configurations

TxBCONF2-

Transmitter User Bit Buffer Configuration

Bit2

Bit1

Zeros are transmitted for the User bits

Host writes User bits to the buffer until it is full

Write the user bits to the buffer in IUs specified by

IEC60958-3 and transmit them according to the

standard

The first 10 bytes of the user bit buffer is

configured to store a Q subcode

Table 24. Transmitter User Bit Buffer Size

TxBCONF0

Buffer Size

384 bits with Preamble Z as the start of the block

768 bits with Preamble Z as the start of the block

The transmit buffers can notify the host or micro-controller

when the first user bit buffer has been updated and when the

second transmit user bit buffer is full using sticky bits and

interrupts. The sticky bit TxUBINT, is set when the transmit

user buffer has been updated and the second transmit user bit

buffer is ready to accept new user bits. The sticky bit, TxFBINT,

is set whenever the second transmit user bit buffer is full and

any new writes to this buffer will be ignored until the first

transmit buffer is updated. These two bits are located in the

Interrupt Status register. When the host reads the Interrupt

Status register these bits will be cleared. Interrupts for the

TxUBINT and TxFBINT sticky bits can be enabled by setting

the TxUBMASK and TxFBMASK bits respectively in the

Interrupt Status Mask register.

0.....7

USER BIT

BUFFER

8.....15

16.....23

TRANSMITTERUSERBIT

INDIRECT ADDRESS

TRANSMITTER USER BIT

DATA REGISTER

ADDRESS = 0x52

ADDRESS = 0x53

0.....7

SECOND

BUFFER

8.....15

16.....23

SPDIF OUT

Figure 32.Transmitter User Bit Buffer

Autobuffering

The ADAV802 SPDIF receiver and transmitter sections have an

autobuffering mode allowing the Channel Status and User bits

to be copied automatically from the receiver to the transmitter

without user intervention. The Channel Status and User bits can

be independently selected for autobuffering using the

Auto_CSBits and Auto_UBits bits in Autobuffer register

respectively. When the receiver and transmitter are running at

the same sample rate the transmitted Channel Status and User

bits will be the same as the received Channel Status and User

bits. However in many systems it is likely that the receiver and

transmitter will not be running at the same frequency. When

the transmitter sample rate is higher than receiver sample rate,

the Channel Status and User bit block may be repeated

sometimes. When the transmitter sample rate is lower than the

receiver sample rate, the Channel Status and User bit blocks

may be dropped. Since the first 5 bytes of the Channel Status

are, typically, constant the can be repeated or dropped and no

information is lost. However, if the PRO bit in the channel

status is set and the local sample address code and time of day

code bytes contain information, these bytes may be repeated or

dropped in which case information can be lost. It is up to the

user to determine how to handle this case. In the case of the

user bits being transmitted according to the IEC60958-3 format

the messages contained in the user bits can still be sent without

dropping or repeating messages. Since zero-stuffing is allowed

between IUs and messages, zeros can be added or subtracted to

preserve the messages. For the case when the transmitter sample

rate is greater than the receiver sample rate extra zeros are

stuffed between the messages. When the sample rate of the

transmitter is less than the sample rate of the receiver, the zeros

stuffed between the messages will be subtracted. If there is not

enough zeros between the messages to be subtracted, the zeros

between IUs will be subtracted as well. The Zero_Stuff_IU bit in

the Autobuffer register enables zeros to be added or subtracted

between messages.

Interrupts

The ADAV802 provides interrupt bits to indicate the presence

of certain conditions which may require attention. Reading the

Interrupt Status register will allow the user to determine if any

of the interrupts have be asserted. The bits of the Interrupt

Status register will remain high, if set, until the register is read.

Two bits, SRCError and RxError indicate interrupt conditions

in the sample rate converter and an SPDIF receiver error

respectively. Both of these condition require a read of the

appropriate error register to determine the exact cause of the

interrupt. Each interrupt in the Interrupt Status register has an

associated mask bit in the Interrupt Status Mask register. The

interrupt mask bit must be set for the corresponding interrupt

to be generated. This feature allows the user to determine which

functions should be responded to. The dual function pin

ZEROL/INT can be set to indicate the presence of no audio

data on the left channel or the presence of an interrupt being set

in the Interrupt Status register. The function of this pin is

selected by the INTRPT bit in DAC Control Register 4 as shown

in Table 25.

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