ADAV802_15 datasheet(22/53 Pages) AD

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ADAV802

Preliminary Technical Data

Rev. Pr G | Page 22 of 53

Sample

Frequency

Emphasis

Lock

Non-

Audio

Pro/Con

Address

Channel Mode

Alignment

Level

Use of Auxiliary Mode

Sample Bits

Channel Identification

Digital Audio

Reference Signal

Sample Frequency (fs)

Reserved

N+1

N+2

N+3

N+4

N+5

Data Bits

User Bit Management

Source Word Length

Res-

erved

Scaling

Alphanumeric Channel Origin Data - First Character

N+6

Alphanumeric Channel Origin Data

N+7

Alphanumeric Channel Origin Data

N+8

Alphanumeric Channel Origin Data - Last Character

N+9

Alphanumeric Channel Destination Data - First Character

N+10

Alphanumeric Channel Destination Data

N+11

Alphanumeric Channel Destination Data

N+12

Alphanumeric Channel Destination Data - Last Character

N+13

Local Sample Address Code - LSW

N+14

Local Sample Address Code

N+15

Local Sample Address Code

N+16

Local Sample Address Code - MSW

N+17

Time Of DayCode- LSW

N+18

Time Of Day Code

N+19

Time Of Day Code

N+20

Time Of Day Code - MSW

N+21

Reserved

N+22

Cyclic Redundancy Check Character (CRCC_

N+23

Reliability Flags

N = 0x20 for Receiver Channel Status Buffer

N = 0x38 for Transmitter Channel Status Buffer

Figure 28. Professional

The standards allow for the channel status bits in each subframe

to be independent, but ordinarily the channel status bit in the

two subframes of each frame are the same. The channel status

bits are defined differently for the consumer audio standards

and the professional audio standards. The 192 channel status

bits are organized into 24 bytes and have the interpretations

shown in Figure 27 and Figure 28.

The SPDIF transmitter and receiver have a comprehensive

functions of the SPDIF block such as detecting non-audio and

validity bits, Q subcodes, preambles etc. The channel status bits

as defined by the IEC60958 and AES3 specification are stored in

for channel status and user bits read by the receiver to be copied

directly to the transmitter block removing the need for user

intervention.

Receiver Section

The ADAV802 uses a double buffering scheme to handle

reading Channel Status and User bit information. The Channel

Status bits are available as a memory buffer taking up 24

consecutive register locations. The User bits are read using an

indirect memory addressing scheme where the Receiver User

Bit Indirect Address register is programmed with an offset to

the User bit buffer and the Receiver User Bit Data register can

be read to determine the User bits at that location. Reading the

Receiver User Bit Data register automatically updates the

Indirect Address Register to the next location in the buffer.

Typically the Receiver User Bit Indirect Address register is

programmed to zero, the start of the buffer, and the Receiver

User Bit Data register is read repeatedly until all the buffers data

has been read. Figure 29 and Figure 30 shows how receiving the

Channel Status and User bits is implemented.

SPDIF

RECEIVE

BUFFER

DIRIN

CHANNEL

STATUS B

(24X 8BITS)

CHANNEL

STATUS A

(24X8BITS)

RECEIVE

CS BUFFER

(0x20-0x37)

RxCSSWITCH

FIRST BUFFER

SECOND BUFFER

Figure 29. Channel Status Buffer

0.....7

USER BIT

BUFFER

8.....15

16.....23

RECEIVER USER BIT

INDIRECT ADDRESS

RECEIVER USER BIT

DATA REGISTER

ADDRESS = 0x50

ADDRESS = 0x51

0.....7

FIRST

BUFFER

8.....15

16.....23

SPDIF IN

801-0032

Figure 30. Receiver User Bit Buffer

The SPDIF receive buffer is updated continuously by the

incoming SPDIF stream and once all of the channel status bits

for the block, 192 for channel A and 192 for channel B, are

received the bits are copied into the receiver channel status

buffer. This buffer stores all 384 bits of channel status

information and the RxCSSWITCH bit in the Channel Status

Switch Buffer register determines whether the channel A or

channel B status bits are required to be read. The receive

channel status bit buffer is 24 bytes long and spans the address

range from 0x20 to 0x37.

Since the Channel Status bits of an SPDIF stream rarely change

a software interrupt/flag bit, RxCSBINT is provided to notify

the host control that either a new block of channel status bits is

available or that the first 5 bytes of channel status information

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