8X930AX datasheet(19/38 Pages) INTEL

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ADVANCE INFORMATION

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER

5.3

Definition of AC Symbols

CC (5)

Active I

PLLSEL = 110

3 MHz – FS

(in low clock mode)

150

PLLSEL = 110

12 MHz – FS

(not in low clock

mode)

PLLSEL = 001

3 MHz – LS

PLLSEL = 100

6 MHz – LS

Table 10. AC Timing Symbol Definitions

Signals

Conditions

Address

High

Data In

Low

ALE

Valid

Data Out

Hold

RD#/PSEN#

Floating

WWR#

Table 9. DC Characteristics at Operating Conditions (Continued)

Symbol

Parameter

Min

Typical (1)

Max

Units

Test Conditions

NOTE:

Typical values are obtained using V

CC = 5.0V, TA = 25°C and are not guaranteed.

Under steady state (non-transient) conditions, I

OL must be externally limited as follows:

Maximum I

OH per port pin:10 mA

Maximum I

OL per 8-bit port:

Port 0: 26 mA

Ports 1-3: 15 mA

Maximum Total I

OL for all output pins: 71 mA

If I

OL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed

to sink current greater than the listed test conditions.

Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level

outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the

Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading

exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify

ALE or other signals with a Schmitt Trigger or CMOS-level input logic.

Capacitive loading on Ports 0 and 2 cause the V

OH on ALE and PSEN to drop below the VCC specifica-

tion when the address lines are stabilizing.

The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.

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