8X930AX datasheet(17/38 Pages) INTEL

17 / 38 page

ADVANCE INFORMATION

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER

5.2

DC Characteristics

Table 9. DC Characteristics at Operating Conditions

Symbol

Parameter

Min

Typical (1)

Max

Units

Test Conditions

Input Low Voltage

(Except EA#)

-0.5

0.2 V

CC – 0.1

Input Low Voltage

(EA#)

00.2 V

CC – 0.3

Input High Voltage

(Except XTAL1, RST)

0.2 V

CC + 0.9

CC + 0.5

Input High Voltage

(XTAL1, RST)

0.7 V

CC + 0.5

Output Low Voltage

(Port 1, 2, 3)

0.3

0.45

1.0

OL = 100 µA (2, 3)

OL = 1.6 mA

OL = 3.5 mA

Output Low Voltage

(Port 0, ALE, PSEN#,

SOF#)

0.3

0.45

1.0

OL = 200 µA (2, 3)

OL = 3.2 mA

OL = 7.0 mA

Output High Voltage

(Port 1, 2, 3,ALE,

PSEN#, SOF#)

CC – 0.3

CC – 0.7

CC – 1.5

OH = -10 µA (4)

OH = -30 µA

OH = -60 µA

Output High Voltage

(Port 0 in External

Address)

CC – 0.3

CC – 0.7

CC – 1.5

OH = -200 µA (4)

OH = -3.2 mA

OH = -7.0 mA

Logical 0 Input

Current (Port 1,2,3)

–150

µA

IN = 0.45 V

Input Leakage Current

(Port 0)

±10

µA

0.45 < V

IN < VCC

NOTE:

Typical values are obtained using V

CC = 5.0V, TA = 25°C and are not guaranteed.

Under steady state (non-transient) conditions, I

OL must be externally limited as follows:

Maximum I

OH per port pin:10 mA

Maximum I

OL per 8-bit port:

Port 0: 26 mA

Ports 1-3: 15 mA

Maximum Total I

OL for all output pins: 71 mA

If I

OL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed

to sink current greater than the listed test conditions.

Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level

outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the

Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading

exceeds 100pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify

ALE or other signals with a Schmitt Trigger or CMOS-level input logic.

Capacitive loading on Ports 0 and 2 cause the V

OH on ALE and PSEN to drop below the VCC specifica-

tion when the address lines are stabilizing.

The abbreviations “LS” and “FS” indicate “Low Speed” and “Full Speed,” respectively.

8X930AX датащи(PDF) 17 Page - Intel Corporation

8X930AX датащи(HTML) 17 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

датащи скачать

ссылки URL