ADVANCE INFORMATION

7

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER

3.0

SIGNALS

Table 5. Signal Descriptions

Signal

Name

Type

Description

Alternate Function

A17

O

18th Address Bit (A17). Output to memory as 18th exter-

nal address bit (A17) in extended bus applications, depend-

ing on the values of bits RD0 and RD1 in configuration byte

UCONFIG0. See also RD#, PSEN#.

P1.7/CEX4/WCLK

A16

O

Address Line 16. See RD#.

RD#

O

Address Lines. Upper address lines for the external bus.

P2.7:0

I/O

Address/Data Lines. Multiplexed lower address lines and

data lines for external memory.

P0.7:0

ALE

O

Address Latch Enable (ALE). ALE signals the start of an

external bus cycle and indicates that valid address informa-

tion is available on lines A15:8 and AD7:0. An external latch

can use ALE to demultiplex the address from the

address/data bus.

PROG#

AV

CC

PWR

Analog V

circuitry.

CEX2:0

CEX3

CEX4

I/O

Programmable Counter Array (PCA) Input/Output Pins.

These are input signals for the PCA capture mode and out-

put signals for the PCA compare mode and PCA PWM

mode.

P1.5:3

P1.6/WAIT#

P1.7/A17/WCLK

D

M

0

I/O

Data Minus. USB minus data line interface.

—

D

P

0

I/O

Data Plus. USB plus data line interface.

—

EA#

I

External Access. Directs program memory accesses to

on-chip or off-chip code memory. For EA# strapped to

ground, all program memory accesses are off-chip. For EA#

strapped to V

address is within the range of the on-chip ROM; otherwise,

the access is off-chip. The value of EA# is latched at reset.

For devices without on-chip ROM, EA# must be strapped to

ground.

ECAP

I

External Capacitor. Must be connected to a 1 µF capacitor

(or larger) to ensure proper operation of the differential line

driver. The other lead of the capacitor must be connected to

V

ECI

I

PCA External Clock Input. External clock input to the 16-

bit PCA timer.

P1.2

INT1:0#

I

External Interrupts 0 and 1. These inputs set bits IE1:0 in

the TCON register. If bits IT1:0 in the TCON register are

set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If

bits INT1:0 are clear, bits IE1:0 are set by a low level on

INT1:0#.

P3.3:2

P0.7:0

I/O

Port 0. This is an 8-bit, open-drain, bidirectional I/O port.

AD7:0

chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 car-

ries the upper address bits (A15:8) and the data (D7:0).