8X930AX datasheet(14/38 Pages) INTEL

14 / 38 page

ADVANCE INFORMATION

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER

†

RD1:0 are bits 3:2 of configuration byte UCONFIG0. Refer to figure 4-3 on page 4-5 in the

8x930Ax Uni-

versal Serial Bus Microcontroller User’s Manual.

4.0

ADDRESS MAP

Table 6. Memory Signal Selections (RD1:0)

RD1:0

†

A17/P1.7

/CEX4/WCLK

A16/P3.7/RD#

PSEN#

WR#

Features

0 0

A17

A16

Asserted for

all addresses

Asserted for writes to

all memory locations

256-Kbyte external

memory

0 1

P1.7/CEX4/WCLK

A16

Asserted for

all addresses

Asserted for writes to

all memory locations

128-Kbyte external

memory

1 0

P1.7/CEX4/WCLK

P3.7 only

Asserted for

all addresses

Asserted for writes to

all memory locations

64-Kbyte external

memory

One additional port

1 1

P1.7/CEX4/WCLK

RD# Asserted

for addresses

≤ 7F:FFFFH

Asserted for

addresses

≥ 80:0000H

Asserted for all com-

patible MCS 51 mem-

ory locations

Compatible with

MCS 51 microcon-

trollers

Table 7. 8

x930Ax Address Map

Internal

Address

Description

Notes

FF:FFFFH

FF:0000H

External Memory: The last eight bytes of the external address range FF:XFF8H–

FF:XFFFH contain configuration byte information.

1, 2, 3

FE:FFFFH

FE:0000H

External Memory

FD:FFFFH

02:0000H

Reserved Addresses

01:FFFFH

01:0000H

External Memory

00:FFFFH

00:0420H

External Memory

00:041FH

00:0080H

On-chip RAM

00:007FH

00:0020H

On-chip RAM

00:001FH

00:0000H

Storage for R0–R7 of Register File

7, 8

NOTES:

Eighteen address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration).

Data in this area is accessible by indirect addressing only.

Eight addresses at the top of all external memory maps are reserved for current and future device

configuration byte information.

This reserved area returns unspecified values and writes no data.

Data is accessible by direct and indirect addressing.

Data is accessible by direct, indirect, and bit addressing.

The special function registers (SFRs) and the register file have separate internal address spaces.

Data is accessible by direct, indirect, and register addressing.

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