REV. B

AD9501

–7–

As shown on the Functional Block Diagram, TTL/CMOS

latches are included to store the digital delay data. Data is

latched when LATCH is HIGH. When LATCH is LOW,

the latches are transparent, and the DAC will attempt to

Figure 5 shows the timing relationship between the input data

30 ns. After the digital (programmed delay) data is updated, a

minimum 30 ns must elapse between the time LATCH goes

HIGH and the arrival of a TRIGGER pulse to assure rated

pulse delay accuracy.

When RESET goes HIGH, the ramp timing capacitor

and overrides the TRIGGER input. Therefore, any trigger pulse

that occurs when RESET is HIGH will not produce an output

pulse. As shown in Figure 5, the next trigger pulse should not

pleted to assure rated pulse delay accuracy.

For most applications, OUTPUT can be tied to RESET.

This causes the output pulse to be narrow (equal to the reset

applied to RESET. To assure a valid output pulse, however, the

delay between TRIGGER and RESET should be equal to or

As shown in Figure 2, the capacitor voltage discharges rapidly

and includes a small amount of overshoot and ringing. Rated timing

delay will not be realized unless subsequent trigger events are

delayed until after the linear ramp settles to its reset voltage value.

The values for the various delay increments in the specification

table are based on a full-scale delay range of 100 ns with OUTPUT

tied to RESET (self-resetting operation).

When full-scale delay range is set for intervals shorter than 100 ns,

the rate of change of the linear ramp is increased. This faster rate

means the maximum trigger rate shown in the specification table

is increased because the ramp generator delay, and consequently,

delay range is decreased. Minimum delays for various full-scale

delay range values are shown in Figure 3.

LATCH

DIGITAL

DATA

TRIGGER

INPUT

RESET

INPUT

OUTPUT

NOTES

A TRIGGERING EVENT MAY OCCUR AT ANY TIME THE DAC (PROGRAMMED DELAY)

IS BEING CHANGED. TRIGGERING EVENTS DURING THE INTERNAL DAC SETTLING

TIME MAY NOT GENERATE AN ACCURATE PULSE DELAY.

– LATCH PULSE WIDTH

– DIGITAL HOLD TIME

– DIGITAL DATA SETUP TIME

– DAC SETTLING TIME

– TRIGGER PULSE WIDTH

– LINEAR RAMP SETTLING TIME

– TRIGGER-TO-RESET HOLD-OFF

– RESET-TO-TRIGGER HOLD-OFF

– RESET PULSE WIDTH

– MINIMUM PROPAGATION DELAY

– RESET PROPAGATION DELAY

– PROGRAMMED DELAY

Figure 5. System Timing

OBSOLETE