REV. B

–5–

AD9501

THEORY OF OPERATION

The AD9501 is a digitally programmable delay device. Its func-

tion is to provide a precise incremental delay between input and

output, proportional to an 8-bit digital word applied to its delay

control port. Incremental delay resolution is 10 ps at the mini-

mum full-scale range of 2.5 ns. Digital delay data inputs, latch,

trigger, and reset are all TTL/CMOS-compatible. Output is

TTL-compatible.

Refer to the AD9501 Functional Block Diagram.

Inside the unit, there are three main subcircuits: a linear ramp

generator, an 8-bit digital-to-analog converter (DAC), and a

voltage comparator. The rising edge of the input (TRIGGER)

pulse initiates the delay cycle by triggering the ramp generator.

The voltage comparator monitors the ramp voltage and switches

the delayed output (Pin 10) HIGH when the ramp voltage crosses

the threshold set by the DAC output voltage. The DAC thresh-

old voltage is programmed by the user with digital inputs.

Figure 2 illustrates in detail how the delay is determined.

generator delay, and comparator delay.

The trigger circuit delay and comparator delay are fixed;

ramp generator delay is a variable affected by the rate of

change of the linear ramp and (to a lesser degree) the value of

the offset voltage described below.

Ramp generator delay is the time required for the ramp to slew

from its reset voltage to the most positive DAC reference volt-

18 mV (with OFFSET ADJUST open) or 34 mV (OFFSET

ADJUST grounded).

RAMP

GENERATOR

TRIGGER

GENERATOR

TRIGGER

DELAYED OUTPUT

RESET

DAC REFERENCE

PROGRAMMED

DAC THRESHOLD

DAC REFERENCE

TRIGGER

CIRCUIT

DELAY

RAMP

GEN.

DELAY

PROGRAMMED

DELAY

FULL-SCALE

DELAY

RANGE

RAMP GEN.

DELAY

PROGRAMMED

DELAY

FULL–SCALE DELAY RANGE

LINEAR RAMP

SETTLING TIME

COMPARATOR

DELAY

RESET PROP

TRIGGER

INPUT

COMPARATOR

DAC

DIGITAL VALUE

256

MINIMUM PROPAGATION DELAY = (

MAXIMUM PROPAGATION DELAY = MINIMUM PROPAGATION DELAY (

PROGRAMMED DELAY (

TOTAL DELAY = (

(100 ns PROGRAMMED DELAY)

Figure 2. Internal Timing

OBSOLETE