AD9501 datasheet(6/12 Pages) AD

6 / 12 page

REV. B

AD9501

–6–

Offset between the two levels is necessary for three reasons.

First, offset allows the ramp to reset and settle without re-entering

the voltage range of the DAC. Second, the DAC may overshoot

as it switches to its most positive value (00H); this can lead to

false output pulses if there is no offset between the ramp reset

voltage and the upper reference. Overshoot on the ramp can also

lead to false outputs without the offset. Finally, the ramp is

slightly nonlinear for a short interval when it is first started;

the offset shifts the most positive DAC level below this

nonlinear region and maintains ramp linearity for short

programmed delay settings.

Pin 8 of the AD9501 is called OFFSET ADJUST (see Func-

tional Block Diagram) and allows the user to control the amount of

offset separating the initial ramp voltage and the most positive

DAC reference. This, in turn, causes the ramp generator delay to

vary.

Figure 3 shows differences in timing that occur if OFFSET

ADJUST Pin 8 is grounded or open. The variable ramp generator

delay is the major component of the three components that

comprise minimum delay (tPD) and, therefore, is affected by the

connection to Pin 8.

It is preferable to ground Pin 8 because the smaller offset that

results from leaving it open increases the possibility of false

output pulses. When grounding the pin, it should be grounded

directly or connected to the ground through a resistor or potentio-

meter with a value of 10 k

W or less.

FULL-SCALE DELAY RANGE – ns

040

400

80 120 160 200 240 280 320 360

CEXT = 0pF

OFFSET ADJUST

(PIN 8) GROUNDED

OFFSET ADJUST

(PIN 8) OPEN

Figure 3. Minimum Delay (tPD) vs. Full-Scale Delay Range (tDFS)

Caution is urged when using resistance in series with Pin 8. The

possibility of false output pulses, as discussed above, is increased

under these circumstances. Using resistance in series with Pin 8

is recommended only when matching minimum delays between

two or more AD9501 devices; it is not recommended if using a

single AD9501. Changing the resistance between Pin 8 and

ground from 0 k

W to 10 kW varies the ramp generator delay by

approximately 35%.

RSET –

10 s

1 s

10ns

100

10k

100ns

10pF

100pF

50pF

0pF

500pF

Figure 4. RC Values vs. Full-Scale Delay Range (tDFS)

The full-scale delay range (tDFS) can be calculated from the

equation:

DFS

SET

EXT

=¥

)

384

Whenever full-scale delay range is 326 ns or less, CEXT should

be left open. Additional capacitance and/or larger values of RSET

increase the linear ramp settling time, which reduces the maxi-

mum trigger rate. When delays longer than 326 ns are required,

up to 500 pF can be connected from CEXT to +VS. To preserve

the unit’s low drift performance, both RSET and CEXT should

have low temperature coefficients. Resistors that are used should

be 1% metal film types.

The programmed delay (tD) is set by the DAC inputs, D0–D7.

The minimum delay through the AD9501 corresponds to an

input code of 00H, and FFH gives the full-scale delay. Any

programmed delay can be approximated by

DAC code

DFS

=¥

)

256

Total delay through the AD9501 for any given DAC code is

equal to

TOTAL

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