ICS1892Y datasheet(43/148 Pages) ICST

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Chapter 7

Functional Blocks

ICS1892, Rev. D, 2/26/01

February 26, 2001

ICS1892

7.3.4

PCS/PMA Receive Modules

Both the PCS and PMA sublayers have Receive modules.

7.3.4.1

PCS Receive Module

The ICS1892 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA

sublayer. The PCS Receive module converts the bit stream from a serial format to a parallel format and

then processes the data to detect the presence of a carrier.

When a link is in the idle state, the PCS Receive module receives IDLE symbols. (All bits are logic one.)

Upon receiving two non-contiguous zeros in the bit stream, the PCS Receive module examines the

ensuing bits and attempts to locate the Start-of-Stream Delimiter (SSD), that is, the /J/K/ symbols.

Upon verification of a valid SSD, the PCS Receive module substitutes the first two standard nibbles of a

Frame Preamble for the detected SSD. In addition, the PCS Receive module uses the SSD to begin

framing the ensuing data into 5-bit code symbols. The final PCS Receive module performs 4B/5B decoding

on the symbols and then synchronously passes the resulting nibbles to the MAC/Repeater Interface.

The Receive state machine continues to accept PMA data, convert it from serial to parallel format, frame it,

decode it, and pass it to the MAC/Repeater Interface. During this time, the Receive state machine

alternates between the Receive and Data States and continues this process until detection of one of the

following:

• An End-of-Stream Delimiter (ESD, that is, the /T/R/ symbols)

• An error

• A premature end (IDLEs)

Upon receipt of an ESD, the Receive state machine returns to the IDLE state without passing the ESD to

the MAC/Repeater Interface. Detection of an error forces the Receive state machine to assert the receive

error signal (RX_ER) and wait for the next symbol. If the ICS1892 Receive state machine detects a

premature end, it forces the assertion of the RX_ER signal, sets the Premature End bit (bit 17.5) to logic

one, and transitions to the IDLE State.

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