LTC6946 datasheet(23/30 Pages) LINER

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LTC6946

6946fa

APPLICATIONS INFORMATION

Divider Programming

Program registers Reg03 to Reg06 with the previously

determined B, R and N divider values.

Reg03 = h00

Reg04 = h50

Reg05 = h4B

Reg06 = h00

VCO ALC and Calibration Programming

Now that all the divider registers are programmed, and

assuming that the reference frequency is stable at REF±,

calibrate the VCO. Set the ALC options (ALCMON = 1,

ALCCAL = 1) and the lock enable bit (LKEN = 1) at the

same time:

Reg07 = h63

The LTC6946 will now calibrate its VCO. The ALC will only

be active during the calibration cycle, but the ALCHI and

ALCLO status conditions will be monitored.

Reference Input Settings and Output Divider

Programming

From Table 1, FILT = 1 for a 20MHz reference frequency.

Next, convert 7dBm into VP-P. For a CW tone, use the

following equation with R = 50:

VP-P ≅ R •10

(dBm – 21)/20

(10)

This gives VP-P = 1.41V, and, according to Table 2, set

BST = 1.

Now program Reg08, assuming maximum RF± output

power (RFO[1:0] = 3 according to Table 9) and OD[2:0] = 2:

Reg08 = hBA

Lock Detect and Charge Pump Current Programming

Next, determine the lock indicator window from fPFD.

From Table 3, LKWIN[1:0] = 3 for a tLWW of 90ns. The

LTC6946 will consider the loop “locked” as long as the

phase coincidence at the PFD is within 8°, as calculated:

phase = 360° • tLWW • fPFD = 360 • 90n • 250k ≅ 8°

LKWIN[1:0] may be set to a smaller value to be more

conservative. However, the inherent phase noise of the

loop could cause false “unlocks” for too small a value.

Choosing the correct LOKCNT depends upon the ratio of

the bandwidth of the loop to the PFD frequency (BW/fPFD).

Smaller ratios dictate larger LOKCNT values. A LOKCNT

value of 128 will work for our ratio of 1/15. From Table 4,

LKCNT[1:0] = 1 for 128 counts.

Using Table 5 with the previously selected ICP of 11.2mA,

gives CP[3:0] = 11 (hB). This is enough information to

program Reg09:

Reg09 = hDB

Charge Pump Function Programming

This example uses the additional voltage clamp features to

allow us to monitor fault conditions by setting CPCHI = 1

and CPCLO = 1. If something occurs and the system can

no longer lock to its intended frequency, the charge pump

output will move toward either GND or VCP+,therebysetting

either the TLO or THI status flags, respectively. Disable all

the other charge pump functions (CPMID, CPINV, CPRST,

CPUP and CPDN) to allow the loop to lock:

Reg0A = hC0

The loop should now lock. Now unmute the output by

setting OMUTE = 0 (assumes the MUTE pin is high):

Reg02 = h08

REFERENCE SOURCE CONSIDERATIONS

A high quality signal must be applied to the REF± inputs as

they provide the frequency reference to the entire PLL. As

mentioned previously, to achieve the part’s in-band phase

noise performance, apply a CW signal of at least 6dBm

into 50Ω, or a square wave of at least 0.5VP-P with slew

rate of at least 40V/μs.

The LTC6946 may be driven single ended to CMOS levels

(greater than 2.7VP-P ). Apply the reference signal directly

without a DC-blocking capacitor at REF+, and bypass

REF– to GND with a 47pF capacitor. The BST bit must also

be set to “0”, according to guidelines given in Table 2.

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