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LTC6946

6946fa

APPLICATIONS INFORMATION

4. Select loop filter components CI and CP based on BW

and RZ. A reliable loop can be achieved by using the

following equations for the loop capacitors (in Farads):

CI =

3.5

2• π •BW •RZ

(8)

CP =

7• π •BW •RZ

(9)

DESIGN AND PROGRAMMING EXAMPLE

This programming example uses the DC1705A with the

LTC6946-3. Assume the following parameters of interest:

fREF = 20MHz at 7dBm into 50Ω

fSTEP = 125kHz

fRF = 2.4GHz

From the Electrical Characteristics table:

fVCO = 3.825GHz to 5.744GHz

KVCO% = 4.0%Hz/V to 6.0%Hz/V

Determining Divider Values

Following the Loop Filter Design algorithm, first deter-

mine all the divider values. Using Equations 2, 3, 4 and 5

calculate the following values:

O = 2

R = 20MHz/(125kHz • 2) = 80

fPFD = 250kHz

N = 2 • 2.4GHz/250kHz = 19200

fVCO = 4.8GHz

Also, from Equation 1 or Table 7 determine B:

B = 8 and BD[3:0] = 0

The next step in the algorithm is to determine the open-

loop bandwidth. BW should be at least 10× smaller than

fPFD. Wider loop bandwidths could have lower integrated

phase noise, depending on the VCO phase noise signature,

while narrower bandwidths will likely have lower spurious

power. Use a factor of 15 for this design example:

BW =

250kHz

= 16.7kHz

Loop Filter Component Selection

Now set loop filter resistor, RZ, and charge pump current,

ICP. Because the KVCO varies over the VCO’s frequency

range, using the KVCO geometric mean gives good results.

Using an ICP of 11.2mA, RZ is determined:

K VCO = 4.8 • 10

9 •0.04 • 0.06 = 235MHz / V

RZ =

2• π • 16.7k • 19200

11.2m • 235M

RZ = 765Ω

Now calculate CI and CP from Equations 7 and 8:

CI =

3.5

2• π • 16.7k • 765

= 44nF

CP =

7• π • 16.7k • 765

= 3.6nF

Status Output Programming

This example will use the STAT pin to alert the system

whenever the LTC6946 generates a fault condition. Pro-

gram x[5], x[4], x[3], x[1], x[0] = 1 to force the STAT pin

high whenever any of the UNLOCK, ALCHI, ALCLO, THI

or TLO flags asserts:

Reg01 = h3B

Power Register Programming

For correct PLL operation all internal blocks should be

enabled, but PDREFO should be set if the REFO pin is

not being used. OMUTE may remain asserted (or the

MUTE pin held low) until programming is complete. For

PDREFO = 1 and OMUTE = 1:

Reg02 = h0A

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