LTC6946 datasheet(20/30 Pages) LINER

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LTC6946

6946fa

OPERATION

STAT Output

The STAT output pin is configured with the x[5:0] bits

of register h01. These bits are used to bit-wise mask, or

enable, the corresponding status flags of status register

h00, according to Equation 2. The result of this bit-wise

Boolean operation is then output on the STAT pin:

STAT = OR (Reg00[5:0] AND Reg01[5:0])

(2)

or expanded:

STAT = (UNLOCK AND x[5]) OR

(ALCHI AND x[4]) OR

(ALCLO AND x[3]) OR

(LOCK AND x[2]) OR

(THI AND x[1]) OR

(TLO AND x[0])

For example, if the application requires STAT to go high

whenever the ALCHI, ALCLO, or THI flags are set, then

x[4], x[3], and x[1] should be set to “1”, giving a register

value of h1A.

Block Power-Down Control

The LTC6946’s power-down control bits are located in

the device may be powered down independently. Care must

be taken with the LSB of the register, the POR (power-on

reset) bit. When written to a “1”, this bit forces a full reset of

the part’s digital circuitry to its power-up default state.

Table 11. Serial Port Register Bit Field Summary

BITS

DESCRIPTION

DEFAULT

ALCCAL

Auto Enable ALC During CAL Operation

ALCEN

Always Enable ALC (Override)

ALCHI

ALC Too Hi Flag

ALCLO

ALC Too Low Flag

ALCMON

Enable ALC Monitor for Status Flags Only

ALCULOK

Enable ALC When PLL Unlocked

BD[3:0]

Calibration B Divider Value

BST

REF Buffer Boost Current

CAL

Start VCO Calibration (auto clears)

CP[3:0]

CP Output Current

CPCHI

CP Enable Hi Voltage Output Clamp

CPCLO

CP Enable Low Voltage Output Clamp

CPDN

CP Pump Down Only

CPINV

CP Invert Phase

CPMID

CP Bias to Mid-Rail

CPRST

CP Three-State

CPUP

CP Pump Up Only

CPWIDE

CP Extend Pulse Width

FILT[1:0]

REF Input Buffer Filter

LKCT[1:0]

PLL Lock Cycle Count

LKEN

PLL Lock Indicator Enable

LKWIN[1:0] PLL Lock Indicator Window

LOCK

PLL Lock Indicator Flag

MTCAL

Mutes Output During Calibration

ND[15:0]

N Divider Value (ND[15:0] > 31)

h00FA

OD[2:0]

Output Divider Value (0 < OD[2:0] < 7)

OMUTE

Mutes RF Output

PART[4:0]

Part code (h01 for LTC6946-1, h02 for

LTC6946-2, h03 for LTC6946-3 Version)

h01, h02, h03

PDALL

Full Chip Power Down

PDOUT

Powers Down O_DIV, RF Output Buffer

PDPLL

Powers Down REF, REFO, R_DIV, PFD,

CPUMP, N_DIV

PDREFO

Powers Down REFO

PDVCO

Powers Down VCO, N_DIV

POR

Force Power-On Reset

RD[9:0]

R Divider Value (RD[9:0] > 0)

h001

REV[2:0]

Rev Code

RFO[1:0]

RF Output Power

THI

CP Clamp High Flag

TLO

CP Clamp Low Flag

UNLOK

PLL Unlock Flag

x[5:0]

STAT Output OR Mask

h04

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