DS2152 datasheet(53/94 Pages) DALLAS

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DS2152

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TCBR1/TCBR2/TCBR3:

TRANSMIT CHANNEL BLOCKING REGISTERS (Address=32 to 34 Hex)

(MSB)

(LSB)

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

TCBR1 (32)

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

TCBR1 (33)

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

TCBR1 (34)

SYMBOL

POSITION

NAME AND DESCRIPTION

CH24

TCBR3.7

Transmit Channel Blocking Registers.

0=force the TCHBLK pin to remain low during this channel

time

CH1

TCBR1.0

1=force the TCHBLK pin high during this channel time

10.0 ELASTIC STORES OPERATION

The DS2152 contains dual two-frame (386 bits) elastic stores, one for the receive direction and one for

the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert

the T1 data stream to 2.048 Mbps (or a multiple of 2.048 Mbps), which is the E1 rate. Secondly, they can

be used to absorb the differences in frequency and phase between the T1 data stream and an

asynchronous (i.e., not frequency locked) backplane clock (which can be 1.544 MHz or 2.048 MHz). The

backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain fully controlled slip

capability, which is necessary for this second purpose. The receive side elastic store can be enabled via

CCR1.2 and the transmit side elastic store is enabled via CCR1.7. The elastic stores can be forced to a

known depth via the Elastic Store Reset bit (CCR3.6). Toggling the CCR3.6 bit forces the read and write

pointers into opposite frames. Both elastic stores within the DS2152 are fully independent and no

restrictions apply to the sourcing of the various clocks that are applied to them. The transmit side elastic

store can be enabled whether the receive elastic store is enabled or disabled and vice versa. Also, each

elastic store can interface to either a 1.544 MHz or 2.048 MHz backplane without regard to the backplane

rate the other elastic store is interfacing.

10.1 RECEIVE SIDE

If the receive side elastic store is enabled (CCR1.2=1), then the user must provide either a 1.544 MHz

(CCR1.3=0) or 2.048 MHz (CCR1.3=1) clock at the RSYSCLK pin. The user has the option of either

providing a frame/multiframe sync at the RSYNC pin (RCR2.3=1) or having the RSYNC pin provide a

pulse on frame boundaries (RCR2.3=0). If the user wishes to obtain pulses at the frame boundary, then

RCR2.4 must be set to 0; if the user wishes to have pulses occur at the multiframe boundary, then

RCR2.4 must be set to 1. The DS2152 will always indicate frame boundaries via the RFSYNC output

whether the elastic store is enabled or not. If the elastic store is enabled, then multiframe boundaries will

be indicated via the RMSYNC output. If the user selects to apply a 2.048 MHz clock to the RSYSCLK

pin, then the data output at RSER will be forced to all 1s every fourth channel and the F-bit will be placed

in the MSB bit position of channel 1. Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12,

16, 20, 24, and 28) will be forced to a 1. Also, in 2.048 MHz applications, the RCHBLK output will be

forced high during the same channels as the RSER pin. See Section 15 for more details. This is useful in

T1 to CEPT (E1) conversion applications. If the 386-bit elastic buffer either fills or empties, a controlled

slip will occur. If the buffer empties, then a full frame of data (193 bits) will be repeated at RSER and the

SR1.4 and RIR1.3 bits will be set to a 1 except the MSB of channel 1. See Figure 15-5. If the buffer fills,

then a full frame of data will be deleted and the SR1.4 and RIR1.4 bits will be set to a 1.

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