DS2152 datasheet(49/94 Pages) DALLAS

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DS2152

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8.1.1 Simple Idle Code Insertion and Per-Channel Loopback

The first method involves using the Transmit Idle Registers (TIR1/2/3) to determine which of the 24 T1

channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).

This method allows the same 8-bit code to be placed into any of the 24 T1 channels. If this method is

used, then the CCR4.0 control bit must be set to 0.

Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in

the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code

contained in the Transmit Idle Definition Register (TIDR). Robbed-bit signaling and Bit 7 stuffing will

occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit

Transparency Registers.

The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per-Channel

Loop-Back (PCLB). If the TIRFS control bit (CCR4.0) is set to 1, then the TIRs will determine which

channels (if any) from the backplane should be replaced with the data from the receive side or, in other

words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must

be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to

TSYNC.

TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=3C to 3E Hex)

[Also used for Per-Channel Loopback]

(MSB)

(LSB)

CH8

CH7

CH6

CH5

CH4

CH3

CH2

CH1

TIR1 (3C)

CH16

CH15

CH14

CH13

CH12

CH11

CH10

CH9

TIR2 (3D)

CH24

CH23

CH22

CH21

CH20

CH19

CH18

CH17

TIR3 (3E)

SYMBOL

POSITION

NAME AND DESCRIPTION

CH24

TIR3.7

Transmit Idle Registers.

0=do not insert the Idle Code in the TIDR into this channel

CH1

TIR1.0

1=insert the Idle Code in the TIDR into this channel

NOTE:

If CCR4.0=1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies

that channel data is to be sourced from the output of the receive side framer (i.e., Per-Channel Loopback;

see Figure 1-1).

TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=3F Hex)

(MSB)

(LSB)

TIDR7

TIDR6

TIDR5

TIDR4

TIDR3

TIDR2

TIDR1

TIDR0

SYMBOL

POSITION

NAME AND DESCRIPTION

TIDR7

TIDR.7

MSB of the Idle Code (this bit is transmitted first)

TIDR0

TIDR.0

LSB of the Idle Code (this bit is transmitted last)

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