CS5126 datasheet(25/32 Pages) CIRRUS

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Sampling Clock Generation Logic

The CS5126 requires an external serial clock to

clock out the data. The CDB5126 board has the

logic necessary to generate the master clock,

HOLD, L/R, and SCLK to allow fast evaluation

of the ADC. In most systems, these timing sig-

nals will be available from the main timing

section, typically generated by a logic array of

some variety. HOLD may be brought in exter-

nally

via

BNC, optionally terminated by R29. SCLK and

L/R select may be brought in externally via test

points and removing jumpers.

Figure 5 shows the on-board clock generation

circuitry. U7 (74HC4040) produces binary di-

vided ratios of the 24.576 MHz master clock. Q4

generates a 1.5 MHz clock, which is used for

SCLK. Q8 generates a 96 kHz clock, used for

HOLD, and Q9 generates a 48 kHz clock, option-

ally used to toggle L/R select. This set of clocks

causes the CS5126 to continuously convert, gen-

erating a continuous stream of serial data bits. To

correctly identify the last bit of each word, U12

produces a pulse only when Q4, Q5, Q6, Q7, Q8,

and optionally Q9 are all high. This state is

latched by U10A to prevent any glitches, and the

resulting signal (attached to TP18) is used to

latch the U8-U9 shift registers.

Serial to Parallel Conversion

Figure 6 shows the serial to parallel conversion

circuit. Two 74HC595 shift register/latches con-

nected in series with SDATA assemble 16-bit,

parallel words, clocked by SCLK. As discussed

above, the outputs are latched inside the

74HC595 at the end of each 16-bit word. The

outputs are brought out to a 40-way header (P5).

Only low capacitance, twisted pair, ribbon cable

should be used.

Q12

Q11

Q10

CLK

RST

OUT

C28

0.1

µF

+5VL

C29

0.1

µF

U11

P10

R28

470

R19

47 k

U12

C32

0.1

µF

U11

C30

0.1

µF

CLR

C31

0.1

µF

311

P12

U11, pin 8

74HC30

74HC00

U10A

74HC73

Crystal

Oscillator

Module

(CLKIN)

(HOLD)

+5VL

U8, U9

Shift CLK

U8, U9

Latch CLK

R18

47 k

R16, p.5

47 k

R16, p.3

47 k

R16

p.4

Figure 5. Timing Generator

CDB5126

DS32DB5

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