поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

CS5126 датащи(PDF) 10 Page - Cirrus Logic

номер детали CS5126
подробное описание детали  16-Bit Stereo A/D Converter for Digital Audio
PDF  32 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5126 датащи(HTML) 10 Page - Cirrus Logic

Back Button CS5126 Datasheet HTML 6Page - Cirrus Logic CS5126 Datasheet HTML 7Page - Cirrus Logic CS5126 Datasheet HTML 8Page - Cirrus Logic CS5126 Datasheet HTML 9Page - Cirrus Logic CS5126 Datasheet HTML 10Page - Cirrus Logic CS5126 Datasheet HTML 11Page - Cirrus Logic CS5126 Datasheet HTML 12Page - Cirrus Logic CS5126 Datasheet HTML 13Page - Cirrus Logic CS5126 Datasheet HTML 14Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 32 page
background image
Simultaneous Sampling
The CS5126 offers four digital output signals,
SSH1, SSH2, TRKL, and TRKR which can be
used to control external sample/hold amplifiers
to achieve simultaneous sampling and/or reduce
sampling distortion.
Figure 7 shows the timing relationships for
SSH1, SSH2, TRKL, and TRKR. In the stereo
configuration shown in Figure 1 the CS5126
samples the left and right channels 180
° out of
phase. Simultaneous sampling between the left
and right channels can be achieved as shown in
Figure 8a using the CS5126’s SSH2 output. The
external sample/hold will freeze the right chan-
nel analog signal as the CS5126 freezes the left
channel input at AINL. It will hold that signal
valid at AINR until the CS5126 begins a right
channel conversion. Once that conversion be-
gins, the sample/hold returns to the sample
mode. The acquisition time for the external sam-
ple/hold amplifier must not exceed the CS5126’s
minimum conversion time of 192 master clock
cycles (7.8
µs for 48kHz stereo sampling).
The CS5126’s sampling distortion with high-fre-
quency, high-amplitude input signals may be im-
proved if a low distortion sample/hold amplifier
is used as shown in Figure 8a. The right channel
input at AINR will appear as dc to the CS5126
resulting in no ac current flowing through the
internal MOS switches. Sampling distortion can
likewise be improved for both channels using
the SSH1 output as shown in Figure 8b. Simi-
AINL
AINR
SSH2
S/H
a. Standard Connections
AINL
AINR
SSH1
S/H
S/H
b. High-Slew Conditions
Figure 8. Simultaneous Sampling Connections
Lch Acq.
Rch Acq.
Rch Convert
Lch Acq.
Lch Convert
Rch Convert
SSH1 (o)
SSH2 (o)
TRKL (o)
TRKR (o)
Acq. & Track
Hold
Acquire & Track
Hold
Internal
Status
L/R (i)
HOLD (i)
Figure 7. External Sampling Control Output Timing
CS5126
10
DS32F1



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com