CS4630

DS445PP1

3

10. CONSUMER IEC-958 DIGITAL INTERFACE (S/PDIF) ...................... 24

11. PCI POWER MANAGEMENT .................................................................. 26

11.1 D0 State ......................................................................................................................... 26

11.2 Dl State .......................................................................................................................... 26

11.3 D2 State ......................................................................................................................... 26

11.4 D3hot State .................................................................................................................... 26

11.6 CS4630 PME# Assertion ............................................................................................... 27

11.6.1 ABITCLK ON ..................................................................................................... 27

11.6.2 ABITCLK OFF ................................................................................................... 27

11.7 On Card Vaux Switching Logic ...................................................................................... 27

12. PIN DESCRIPTION ............................................................................................................... 29

12.1 PCI Interface .................................................................................................................. 30

12.2 PCI Power Management Interface Pins ........................................................................ 31

12.3 External Interface Pins .................................................................................................. 32

12.4 Clock / Miscellaneous .................................................................................................... 33

12.5 Serial Codec Interface ................................................................................................... 34

12.6 ZV Port Serial Interface ................................................................................................. 35

12.7 Consumer Digital Audio I/O (S/PDIF) ............................................................................ 35

12.8 Asynchronous Serial Interface and Enhanced General Purpose I/O ............................ 36

13. PACKAGE OUTLINE ................................................................................ 37

LIST OF FIGURES

Figure 1.

AC Characteristics ...................................................................................................... 5

Figure 2.

PCI Timing Measurement Conditions ......................................................................... 7

Figure 3.

AC ’97 Configuration Timing Diagram ........................................................................ 8

Figure 4.

ZV PORT .................................................................................................................... 9

Figure 5.

Independent Timing Configuration ........................................................................... 10

Figure 6.

EEPROM Timing ...................................................................................................... 11

Figure 7.

CS4630 Block Diagram ............................................................................................ 12

Figure 8.

AC ‘97 Codec Interface ............................................................................................ 14

Figure 9.

Portable Docking Station Scenario ........................................................................... 14

Figure 10. Host Interface Base Address Registers .................................................................... 15

Figure 11. AC ‘97 Codec Connection Diagram .......................................................................... 20

Figure 12. Dual AC ‘97 Codec Connection Diagram ................................................................. 21

Figure 13. Joystick Logic ........................................................................................................... 22

Figure 14. External EEPROM Connection ................................................................................. 23

Figure 15. EEPROM Read Sequence ....................................................................................... 23

Figure 16. ZV Port Clocking Format .......................................................................................... 24

Figure 17. IEC Consumer Interface Implementation Circuit ...................................................... 25

Figure 18. Optional Fiber Optic Circuit ...................................................................................... 25

Figure 19. On-Card 3.3Vaux Switching Logic ............................................................................ 28