CS4630

DS445PP1

11

2.5V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V, Logic 1 = 3.3 V;

Timing reference levels = 1.4 V; PCI clock frequency = 33 MHz; unless otherwise noted (Note 4))

Notes: 19. Rise time on EEDAT is determined by the capacitance on the EEDAT line with all connected gates and

the required external pull-up resistor. Nominal values based on 4.7k and 22pF.

Parameter

Symbol

Min

Max

Units

EECLK Low to EEDAT Data Out Valid

07.0

µs

Start Condition Hold Time

5.0

-

µs

EECLK Low

10

-

µs

EECLK High

10

-

µs

Start Condition Setup Time (for a Repeated Start Condition)

5.0

-

µs

EEDAT In Hold Time

0-

µs

EEDAT In Setup Time

250

-

ns

EEDAT/EECLK Rise Time

(Note 19)

-1

µs

EEDAT/EECLK Fall Time

-

300

ns

Stop Condition Setup Time

5.0

-

µs

EEDAT Out Hold Time

0-

µs

EECLK

EEDAT (IN)

EEDAT (OUT)

t

F

t

R

t

SU:STA

t

HD:STA

t

HD:DAT

t

SU:DAT

t

SU:STO

t

AA

t

DH

t

HEECLK

t

LEECLK

EEDAT (OUT)

Figure 6. EEPROM Timing