CS4298 datasheet(43/52 Pages) CIRRUS

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CS4298

DS315PP2

8.1

Digital I/O Pins

RESET# - AC ’97 Chip Reset, Input

This active low signal is the asynchronous Cold Reset input to the CS4298. The CS4298 must

be reset before it can enter normal operating mode. When the PR4 bit of register 26h is set, the

RESET# rising edge will be used as an AC ‘97 2.1 Warm Reset only, preserving register

values.

SYNC - AC-link Serial Port Sync pulse, Input

This signal is the serial port timing signal for the AC-link of the CS4298. Its period is the

reciprocal of the sample rate of the CS4298, 48 kHz. This signal is generated by the AC ’97

Controller and is synchronous to BIT_CLK. SYNC is also an asynchronous input when the

CS4298 is in a PR4 powerdown state and is configured as a primary codec. A series

terminating resistor of 47

Ω should be connected on this signal close to the device driving the

signal.

BIT_CLK - AC-link Serial Port Master Clock, Input/Output

This input/output signal controls the master clock timing for the AC-link. In codec primary

mode, this signal is an output 12.288 MHz clock signal which is divided down by two from the

XTL_IN input clock pin. In codec secondary mode, this signal is an input which controls the

AC-link serial interface. In BIT_CLK mode, this signal generates all internal clocking including

the AC-link serial interface timing. A series terminating resistor of 47

Ω should be connected

on this signal close to the CS4298 in primary mode or close to the BIT_CLK source if in

secondary mode.

SDATA_OUT - AC-link Serial Data Input Stream to AC ‘97, Input

This input signal transmits the control information and digital audio output streams to be sent

to the DACs. The data is clocked into the CS4298 on the falling edge of BIT_CLK. A series

terminating resistor of 47

Ω should be connected on this signal close to the device driving the

input.

SDATA_IN - AC-link Serial Data Output Stream from AC ‘97, Output

This output signal transmits the status information and digital audio input streams from the

ADCs. The data is clocked out of the CS4298 on the rising edge of BIT_CLK. A series

terminating resistor of 47

Ω should be connected on this signal as close to the CS4298 as

possible.

XTL_IN - Crystal Input

This pin accepts either a crystal, with the other pin attached to XTL_OUT, or an external

CMOS clock. XTL_IN must have a crystal or clock source attached for proper operation except

when operating in BIT_CLK mode. The crystal frequency must be 24.576 MHz and designed

for fundamental mode, parallel resonance operation.

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