CS4298 datasheet(17/52 Pages) CIRRUS

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CS4298

DS315PP2

5.3

AC-Link AudioOutput Frame

5.3.1

Serial Data Output Slot Tags (Slot 0)

Valid FrameDetermines if any of the following slots contain either valid playback data for the Codec’s DACs, data

for read/write operation, or GPIO data. When set, at least one of the other AC-link slots contain valid

data. If this bit is clear, the remainder of the frame is ignored.

Slot [1:2] ValidIndicates valid slot data when accessing the register set of the primary Codec (SCRA[1:0] = 00). For

a read operation, Slot 1 Valid is set when

eration, Slot 1 Valid and Slot 2 Valid are set indicating

(Slot 2) contain valid data. The register address and write data must be valid within the same frame.

SCRA[1:0] must be cleared when accessing the primary Codec. The physical address of a Codec is

determined by the ID[1:0]# input pins which are reflected in the

Extended Audio ID (Index 28h) register

and the

Extended Modem ID (Index 3Ch) register.

Slot [3:11] Valid

If a Slot Valid bit is set, the named slot contains valid audio data. If the bit is clear, the slot will be ignored.

The definition of each slot is determined by the basic operating mode selected for the CS4298. For more

information, see the

AC Mode Control (Index 5Eh) register.

Slot 12 ValidIf Slot 12 Valid is set, Slot 12 contains valid write data for the GPIO pins.

SCRA[1:0] Secondary Codec Register Access. Unlike the primary Codec, SCRA[1:0] indicate valid slot data when

accessing the register set of a secondary Codec. The value set in SCRA[1:0] (01,10,11) determines

which of the three possible secondary Codecs is accessed. For a read operation, the SCRA[1:0] bits

are set when

set when

ation requires the register address and the write data to be valid within the same frame. SCRA[1:0] must

be cleared when accessing the primary Codec. They must also be cleared during the idle period where

no register read or write is pending. The physical address of a Codec is determined by the ID[1:0]# input

pins which are reflected in the

Extended Audio ID (Index 28h) register and the Extended Modem ID (In-

dex 3Ch) register. The SCRA[1:0] bits are listed as the ID[1:0] bits in Slot 0 in the AC ‘97 specification.

5.3.2

R/W #

Read/Write#. Determines if a read (R/W# = 1) or write (R/W# = 0) operation is requested. For a read

operation, the following Input Frame will return the register index in the

Read-Back Address Port (Slot

1) and the contents of the register in the

Read-Back Data Port (Slot 2). A write operation does not return

any valid data in the following frame. If the R/W# bit = 0, data must be valid in both the

(Slot 1) and the

RI[6:0]

RI[6:0] must contain valid data during a frame when the Slot 1 Valid or SCRA[1:0] are set.

Bit 15

76543210

Valid

Frame

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

Slot 10

Valid

Slot 11

Valid

Slot 12

Valid

SCRA

Bit 19

98765

43210

R/W# RI6

RI5

RI4

RI3

RI2

RI1

RI0

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