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AD9524/PCBZ датащи(PDF) 24 Page - Analog Devices

номер детали AD9524/PCBZ
подробное описание детали  Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs
PDF  56 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9524/PCBZ датащи(HTML) 24 Page - Analog Devices

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AD9524
Data Sheet
Rev. E | Page 24 of 56
Clock Distribution Synchronization
A block diagram of the clock distribution synchronization
functionality is shown in Figure 27. The synchronization
sequence begins with the primary synchronization signal,
which ultimately results in delivery of a synchronization strobe
to the clock distribution logic.
As indicated, the primary synchronization signal originates
from one of the following sources:
Direct synchronization source via the sync dividers bit (see
Register 0x232, Bit 0 in Table 56)
Device pin, SYNC (Pin 13)
An automatic synchronization of the divider is initiated the first
time that PLL2 locks after a power-up or reset event. Subsequent
lock/unlock events do not initiate a resynchronization of the
distribution dividers unless they are preceded by a power-down
or reset of the part.
FAN OUT
VCO OUTPUT DIVIDER
SYNC (PIN 13)
SYNC
DIVIDER
DRIVER
OUTx
OUTx
OUT
SYNC
PHASE
DIVIDE
SYNC DIVIDERS BIT
Figure 27. Clock Output Synchronization Block Diagram
DIVIDE = 2, PHASE = 0
DIVIDE = 2, PHASE = 6
VCO DIVIDER OUTPUT CLOCK
SYNC
CONTROL
6 × 0.5 PERIODS
Figure 28. Clock Output Synchronization Timing Diagram



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