поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

AD9524/PCBZ датащи(PDF) 53 Page - Analog Devices

номер детали AD9524/PCBZ
подробное описание детали  Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs
PDF  56 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9524/PCBZ датащи(HTML) 53 Page - Analog Devices

Back Button AD9524/PCBZ Datasheet HTML 48Page - Analog Devices AD9524/PCBZ Datasheet HTML 49Page - Analog Devices AD9524/PCBZ Datasheet HTML 50Page - Analog Devices AD9524/PCBZ Datasheet HTML 51Page - Analog Devices AD9524/PCBZ Datasheet HTML 52Page - Analog Devices AD9524/PCBZ Datasheet HTML 53Page - Analog Devices AD9524/PCBZ Datasheet HTML 54Page - Analog Devices AD9524/PCBZ Datasheet HTML 55Page - Analog Devices AD9524/PCBZ Datasheet HTML 56Page - Analog Devices  
Zoom Inzoom in Zoom Outzoom out
 53 / 56 page
background image
Data Sheet
AD9524
Rev. E | Page 53 of 56
Address
Bits
Bit Name
Description
0x231
[7:6]
Reserved
Reserved.
[5:0]
Status Monitor 1 control
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Muxout
0
0
0
0
0
0
GND
0
0
0
0
0
1
PLL1 and PLL2 locked
0
0
0
0
1
0
PLL1 locked
0
0
0
0
1
1
PLL2 locked
0
0
0
1
0
0
Both references are missing (REFA and REFB)
0
0
0
1
0
1
Both references are missing and PLL2 is locked
0
0
0
1
1
0
REFB selected (applies only to auto select mode)
0
0
0
1
1
1
REFA is OK
0
0
1
0
0
0
REFB is OK
0
0
1
0
0
1
REF_TEST is OK
0
0
1
0
1
0
VCXO is OK
0
0
1
0
1
1
PLL1 feedback is OK
0
0
1
1
0
0
PLL2 reference clock is OK
0
0
1
1
0
1
Reserved
0
0
1
1
1
0
REFA and REFB are OK
0
0
1
1
1
1
All clocks are OK (except REF_TEST)
0
1
0
0
0
0
GND
0
1
0
0
0
1
GND
0
1
0
0
1
0
GND
0
1
0
0
1
1
GND
0
1
0
1
0
0
PLL2 feedback is divide-by-2
0
1
0
1
0
1
PLL2 PFD down divide-by-2
0
1
0
1
1
0
PLL2 REF divide-by-2
0
1
0
1
1
1
PLL2 PFD up divide-by-2
Note that all bit combinations after 010111 are reserved.
0x232
[7:5]
Reserved
Reserved.
4
Enable Status_EEPROM
on STATUS0 pin
Enables the EEPROM status on the STATUS0 pin.
1: enable status.
3
STATUS1 pin divider
enable
Enables a divide-by-4 on the STATUS1 pin, allowing dynamic signals to be viewed at a lower
frequency (such as the PFD input clocks). Not to be used with dc states on the status pins,
which occur when the settings of Register 0x231, Bits[5:0] are in the range of 000000 to 001111.
1: enabled.
0: disabled.
2
STATUS0 pin divider
enable
Enables a divide-by-4 on the STATUS0 pin, allowing dynamic signals to be viewed at a lower
frequency (such as the PFD input clocks). Not to be used with dc states on the status pins,
which occur when the settings of Register 0x230, Bits[5:0] are in the range of 000000 to 001111.
1: enable.
0: disable.
1
Reserved
Reserved.
0
Sync dividers
(manual control)
Set bit to put dividers in sync; clear bit to release. Functions like SYNC pin low.
1: sync.
0: normal.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com