LPC2131 datasheet(19/45 Pages) PHILIPS

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LPC2131_32_34_36_38

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Product data sheet

Rev. 5.1 — 29 July 2011

19 of 45

NXP Semiconductors

LPC2131/32/34/36/38

Single-chip 16/32-bit microcontrollers

6.12.1 Features

• Compliant with Serial Peripheral Interface (SPI) specification.

• Synchronous, Serial, Full Duplex, Communication.

• Combined SPI master and slave.

• Maximum data bit rate of one eighth of the input clock rate.

6.13 SSP serial I/O controller

The LPC2131/32/34/36/38 each contain one Serial Synchronous Port controller (SSP).

The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. However, only a single master and a

single slave can communicate on the bus during a given data transfer. The SSP supports

full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. Often only one of these data flows carries

meaningful data.

6.13.1 Features

• Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire

buses.

• Synchronous Serial Communication.

• Master or slave operation.

• 8-frame FIFOs for both transmit and receive.

• Four bits to 16 bits per frame.

6.14 General purpose timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an

externally supplied clock, and optionally generate interrupts or perform other actions at

specified timer values, based on four match registers. It also includes four capture inputs

to trap the timer value when an input signal transitions, optionally generating an interrupt.

Multiple pins can be selected to perform a single capture or match function, providing an

application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.

At any given time only one of peripheral’s capture inputs can be selected as an external

event signal source, i.e., timer’s clock. The rate of external events that can be

successfully counted is limited to PCLK/2. In this configuration, unused capture lines can

be selected as regular timer capture inputs.

6.14.1 Features

• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.

• External Event Counter or timer operation.

• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer

value when an input signal transitions. A capture event may also optionally generate

an interrupt.

• Four 32-bit match registers that allow:

– Continuous operation with optional interrupt generation on match.

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