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PD720201 датащи(PDF) 20 Page - Renesas Technology Corp

номер детали PD720201
подробное описание детали  ASSP (USB3.0 HOST CONTROLLER)
PDF  43 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

PD720201 датащи(HTML) 20 Page - Renesas Technology Corp

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μPD720201/μPD720202
3. ELECTRICAL SPECIFICATIONS
R19DS0047EJ0500 Rev. 5.00
Page 20 of 40
Jan. 17, 2013
3.8.3
Reset
Table 3-11.
Power on Reset (PONRSTB) Timings
Parameter
Symbol
Condition
Min.
Max.
Units
Power on reset time
TPONRST
See Figure 3-9
1
ms
Remarks 1. There is no order to power-on of VDD33, AVDD33, AVDD33 and VDD10.
2. All power sources should be stable within 100 ms from the fastest rising edge of power sources.
3. PONRSTB shall be de-asserted after all power sources and the system clock become stable.
4. PONRSTB shall be de-asserted before de-asserting PERSTB.
Table 3-12.
PCI Express Interface - PERSTB Signal Timings
Parameter
Symbol
Condition
Min.
Max.
Units
Power stable to PERSTB inactive
T
PVPERL
See Figure 3-9
100
ms
PECLKP/PECLKN stable before PERSTB
inactive
T
PERST-CLK
See Figure 3-9
100
μs
Figure 3-9.
Power Up and Reset
Remark As a power saving feature, the
μPD720201 / μPD720202 stops XT1/XT2 oscillation whenever PERSTB is
asserted (low) while PONRSTB is inactive (high).
XT1/XT2 oscillation does not stop while PONRSTB is
asserted (low).



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