μPD720201/μPD720202

3. ELECTRICAL SPECIFICATIONS

R19DS0047EJ0500 Rev. 5.00

Page 17 of 40

Jan. 17, 2013

3.8

AC Characteristics

3.8.1

System Clock

Table 3-9.

System clock (XT1/XT2) ratings

Parameter

Symbol

Condition

Min.

Typ.

Max.

Units

Clock frequency

F

CLK

Crystal

−100

ppm

24

+100

ppm

MHz

Clock duty cycle

T

DUTY

40

50

60

%

Remark Required accuracy of crystal or oscillator block includes initial frequency accuracy, the spread of Crystal

capacitor loading, supply voltage, temperature and aging, etc.

3.8.2

PCI Express Reference Clock

Table 3-10.

PCI Express Interface - Reference Clock (PECLKP and PECLKN) Timings

Parameter

Symbol

Condition

Min.

Max.

Units

Rising Edge Rate

T

RISE

See Figure 3-5

0.6

4.0

V/ns

Falling Edge Rate

T

FALL

See Figure 3-5

0.6

4.0

V/ns

Differential Input High Voltage

V

IH

See Figure 3-8

+150

mV

Differential Input Low Voltage

V

IL

See Figure 3-8

−150

mV

Absolute crossing point voltage

V

CROSS

See Figure 3-3

+250

+550

mV

Variation of V

V

CROSS DELTA

See Figure 3-4

+140

mV

Ring-back Voltage Margin

V

RB

See Figure 3-8

−100

+100

mV

Time before V

T

STABLE

See Figure 3-8

500

ps

Average Clock Period Accuracy

T

PERIOD AVG

−300

+2800

ppm

Absolute Period (including Jitter and

Spread Spectrum)

T

PERIOD ABS

9.847

10.203

ns

Cycle to Cycle Jitter

V

CCJITTER

150

ps

Absolute Max input voltage

V

MAX

See Figure 3-3

+1.15

V

Absolute Min input voltage

V

MIN

See Figure 3-3

−0.3

V

Duty Cycle

See Figure 3-6

40

60

%

Rising edge rate (PECLKP) to falling edge

rate (PECLKN) matching

See Figure 3-7

20

%

Clock source DC impedance

Z

C-DC

See Figure 3-2

40

60

Ω