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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PD720201 датащи(PDF) 4 Page - Renesas Technology Corp |
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PD720201 датащи(HTML) 4 Page - Renesas Technology Corp |
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4 / 43 page  μPD720201/μPD720202 1. OVERVIEW R19DS0047EJ0500 Rev. 5.00 Page 4 of 40 Jan. 17, 2013 1.4 Block Diagram Figure 1-1. μPD720201 Block Diagram Figure 1-2. μPD720202 Block Diagram PCI Express Gen2 Interface Complies with PCI Express Gen2 interface, with 1 lane. This block includes both the link and PHY layers. xHCI Controller Handles all support required for USB 3.0, SuperSpeed and Hi-/Full-/Low-speed. This block includes the register interface from the system. Root hub Hub function in host controller. SS PHY For SuperSpeed Tx/Rx HS/FS/LS PHY For Hi-/Full-/Low-Speed Tx/Rx Power SW I/F Connected to external power switch for port power control and over current detection. SPI Interface Connected to external serial ROM. When system BIOS or system software does not support FW download function, the external serial ROM is required. OSC Internal oscillator block. |
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