PD720201 datasheet(10/43 Pages) RENESAS

10 / 43 page

μPD720201/μPD720202

2. PIN FUNCTION

R19DS0047EJ0500 Rev. 5.00

Page 10 of 40

Jan. 17, 2013

Pin Name

720201

Pin No.

720202

Pin No.

I/O

Type

Active

Level

Function

U3TXDP3

−

(USB3)

−

USB3.0 Transmit data D+ signal for SuperSpeed

U3TXDN3

−

(USB3)

−

USB3.0 Transmit data D- signal for SuperSpeed

U3RXDP3

−

(USB3)

−

USB3.0 Receive data D+ signal for SuperSpeed

U3RXDN3

−

(USB3)

−

USB3.0 Receive data D- signal for SuperSpeed

U2DP3

−

I/O

(USB2)

−

USB2.0 D

+ signal for Hi-/Full-/Low-Speed

U2DM3

−

I/O

(USB2)

−

USB2.0 D

− signal for Hi-/Full-/Low-Speed

OCI3B

−

(3.3 V

Input)

Low

Over-current status input signal.

0: Over-current condition is detected

1: No over-current condition is detected

PPON3

−

(3.3 V

Output)

High

USB port power supply control signal.

0: Power supply OFF

1: Power supply ON

U3TXDP4

−

(USB3)

−

USB3.0 Transmit data D+ signal for SuperSpeed

U3TXDN4

−

(USB3)

−

USB3.0 Transmit data D- signal for SuperSpeed

U3RXDP4

−

(USB3)

−

USB3.0 Receive data D+ signal for SuperSpeed

U3RXDN4

−

(USB3)

−

USB3.0 Receive data D- signal for SuperSpeed

U2DP4

−

I/O

(USB2)

−

USB2.0 D

+ signal for Hi-/Full-/Low-Speed

U2DM4

−

I/O

(USB2)

−

USB2.0 D

− signal for Hi-/Full-/Low-Speed

OCI4B

−

(3.3 V

Input)

Low

Over-current status input signal.

0: Over-current condition is detected

1: No over-current condition is detected

PPON4

−

(3.3 V

Output)

High

USB port power supply control signal.

0: Power supply OFF

1: Power supply ON

Note 1: The SuperSpeed signals (U3TXDPx, U3TXDNx, U3RXDPx, U3RXDNx) and high-/full-/low-signals

(U2DPx, U2DMx) of

μPD720201 and μPD720202 shall be connected to the same USB connecter,

Refer to

μPD720201/μPD720202 User’s Manual.

Note 2: The Timing of PPONx assertion is changed from

μPD720200. The PPONx of μPD720200A,

μPD720201 and μPD720202 are asserted after the software sets Max Device Slots

Enable(MaxSlotsEn) field in Configure(CONFIG) register or Host Controller Reset(HCRST) flag in

USBCMD register. On

μPD720200, the PPON(2:1) are asserted immediately after the PCIe Reset.

Regarding the CONFIG and USBCMD register, refer to the

μPD720201/μPD720202 User's Manual.

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