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PSD833F2 датащи(PDF) 112 Page - STMicroelectronics

номер детали PSD833F2
подробное описание детали  Flash in-system programmable (ISP) peripherals
PDF  128 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD833F2 датащи(HTML) 112 Page - STMicroelectronics

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AC/DC parameters
PSD8XXFX
112/128
Doc ID 7833 Rev 7
Figure 47.
Peripheral I/O WRITE timing
Table 63.
Port A Peripheral Data mode READ timing (3V devices)
Symbol
Parameter
Conditions
-12
-15
-20
Turbo
off
Unit
Min Max Min Max Min
Max
tAVQV–PA
Address valid to data valid
(1)
50
50
50
+ 20
ns
tSLQV–PA
CSI valid to data valid
37
45
50
+ 20
ns
tRLQV–PA
RD to data valid
(2)(3)
37
40
45
ns
RD to data valid 8031 mode
45
45
50
ns
tDVQV–PA
Data In to data Out valid
38
40
45
ns
tQXRH–PA
RD data hold time
0
0
0
ns
tRLRH–PA
RD pulse width
(2)
36
36
46
ns
tRHQZ–PA
RD to data high-Z
(2)
36
40
45
ns
1.
Any input used to select port A Data Peripheral mode.
2.
RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
3.
Data is already stable on port A.
tDVQV (PA)
tWLQV
(PA)
tWHQZ (PA)
ADDRESS
DATA OUT
A / D BUS
WR
PORT A
DATA OUT
ALE /AS
AI02898
Table 64.
Port A Peripheral Data mode WRITE timing (5 V devices)
Symbol
Parameter
Conditions
-70
-90
-15
Unit
Min Max Min
Max Min Max
tWLQV–PA
WR to data propagation delay
(1)
25
35
40
ns
tDVQV–PA
Data to port A data propagation delay
(2)
22
30
38
ns
tWHQZ–PA
WR invalid to port A tri-state
(1)
20
25
33
ns
1.
WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
2.
Data stable on ADIO pins to data on port A.
Obsolete
Product(s)
- Obsolete
Product(s)



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