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PSD833F2 датащи(PDF) 111 Page - STMicroelectronics

номер детали PSD833F2
подробное описание детали  Flash in-system programmable (ISP) peripherals
PDF  128 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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PSD833F2 датащи(HTML) 111 Page - STMicroelectronics

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PSD8XXFX
AC/DC parameters
Doc ID 7833 Rev 7
111/128
Figure 46.
Peripheral I/O READ timing
1.
The whole memory is programmed to 00h before erase.
2.
The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
tQXRH (PA)
tRLQV (PA)
tRLRH (PA)
tDVQV (PA)
tRHQZ (PA)
tSLQV (PA)
tAVQV (PA)
ADDRESS
DATA VALID
ALE /AS
A /D BUS
RD
DATA ON PORT A
CSI
AI02897
Table 62.
Port A Peripheral Data mode READ timing (5 V devices)
Symbol
Parameter
Conditions
-70
-90
-15
Turbo
off
Unit
Min Max Min Max Min
Max
tAVQV–PA
Address valid to data valid
(1)
37
39
45
+ 10
ns
tSLQV–PA
CSI valid to data valid
27
35
45
+ 10
ns
tRLQV–PA
RD to data valid
(2)(3)
21
32
40
ns
RD to data valid 8031 mode
32
38
45
ns
tDVQV–PA
Data In to data out valid
22
30
38
ns
tQXRH–PA
RD data hold time
0
0
0
ns
tRLRH–PA
RD pulse width
(2)
27
32
38
ns
tRHQZ–PA
RD to data high-Z
(2)
23
25
30
ns
1.
Any input used to select port A Data Peripheral mode.
2.
RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
3.
Data is already stable on port A.
Obsolete
Product(s)
- Obsolete
Product(s)



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