PSD833F2 datasheet(109/128 Pages) STMICROELECTRONICS

109 / 128 page

PSD8XXFX

AC/DC parameters

Doc ID 7833 Rev 7

109/128

tWHPV

Trailing edge of WR to port output

valid using I/O port data register

(2)

tDVMV

Data valid to port output valid

using macrocell register

Preset/Clear

(2)(4)

tAVPV

Address input valid to address

output delay

(5)

tWLMV

WR valid to port output valid using

macrocell register Preset/Clear

(2)(6)

Any input used to select an internal PSD function.

WR has the same timing as E, LDS, UDS, WRL, and WRH signals.

tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.

Assuming WRITE is active before data becomes valid.

In multiplexed mode, latched address generated from ADIO delay to address output on any port.

Assuming data is stable before active WRITE signal.

Table 58.

WRITE timing (5 V devices) (continued)

Symbol

Parameter

Conditions

-70

-90

-15

Unit

Min Max Min

Max Min Max

Table 59.

WRITE timing (3 V devices)

Symbol

Parameter

Conditions

-12

-15

-20

Unit

MinMax MinMax

MinMax

tLVLX

ALE or AS pulse width

tAVLX

Address setup time

(1)

910

tLXAX

Address hold time

(1)

912

tAVWL

Address valid to Leading

Edge of WR

(1)(2)

tSLWL

CS valid to Leading Edge of WR

(2)

tDVWH

WR data setup time

(2)

tWHDX

WR data hold time

(2)

tWLWH

WR pulse width

(2)

tWHAX1

Trailing edge of WR to address invalid

(2)

tWHAX2

Trailing edge of WR to DPLD address

invalid

(2)(3)

tWHPV

Trailing edge of WR to port output

valid using I/O port data register

(2)

tDVMV

Data valid to port output valid

using macrocell register Preset/Clear

(2)(4)

Obsolete

Product(s)

- Obsolete

Product(s)

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