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PSD833F2 датащи(PDF) 100 Page - STMicroelectronics

номер детали PSD833F2
подробное описание детали  Flash in-system programmable (ISP) peripherals
PDF  128 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD833F2 датащи(HTML) 100 Page - STMicroelectronics

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AC/DC parameters
PSD8XXFX
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Doc ID 7833 Rev 7
Figure 39.
Input to output disable / enable
tER
tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
Table 48.
CPLD combinatorial timing (5 V devices)
Symbol
Parameter
Conditions
-70
-90
-15
Fast
PT
Aloc
Turbo
off
Slew
rate
(1)
Unit
MinMax MinMax MinMax
tPD
CPLD input
pin/feedback to
CPLD combinatorial
output
20
25
32
+ 2
+ 10
– 2
ns
tEA
CPLD input to CPLD
output enable
21
26
32
+ 10
– 2
ns
tER
CPLD input to CPLD
output disable
21
26
32
+ 10
– 2
ns
tARP
CPLD register clear
or preset delay
21
26
33
+ 10
– 2
ns
tARPW
CPLD register clear
or preset pulse width
10
20
29
+ 10
ns
tARD
CPLD array delay
Any
macrocell
11
16
22
+ 2
ns
1.
Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
Table 49.
CPLD combinatorial timing (3 V devices)
Symbol
Parameter
Conditions
-12
-15
-20
PT
Aloc
Turbo
off
Slew
rate
(1)
Unit
Min Max Min Max Min Max
tPD
CPLD input
pin/feedback to
CPLD combinatorial
output
40
45
50
+ 4
+ 20
– 6
ns
tEA
CPLD input to CPLD
output enable
43
45
50
+ 20
– 6
ns
tER
CPLD input to CPLD
output disable
43
45
50
+ 20
– 6
ns
tARP
CPLD register clear
or preset delay
40
43
48
+ 20
– 6
ns
Obsolete
Product(s)
- Obsolete
Product(s)



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