AM79C976 datasheet(186/309 Pages) AMD

186 / 309 page

186

Am79C976

8/01/00

P R E L I M INARY

DRTY

Disable Retry. When DRTY is set

to 1, the Am79C976 controller will

attempt only one transmission. In

this mode, the device will not pro-

tect the first 64 bytes of frame

data in the Transmit FIFO from

being overwritten, because auto-

matic retransmission will not be

necessary. When DRTY is set to

0, the Am79C976 controller will

attempt 16 transmissions before

signaling a retry error.

Read/Write accessible.

FCOLL

Force Collision. This bit allows

the collision logic to be tested.

The Am79C976 controller must

be in internal loopback for FCOLL

to be valid. If FCOLL = 1, a colli-

sion will be forced during loop-

back

transmission

attempts,

which will result in a Retry Error.

If FCOLL = 0, the Force Collision

logic will be disabled. FCOLL is

defined

after

the

initialization

block is read.

Read/Write accessible.

DXMTFCS

Disable Transmit CRC (FCS).

When DXMTFCS is set to 0, the

transmitter will generate and ap-

pend an FCS to the transmitted

frame. When DXMTFCS is set to

1, no FCS is generated or sent

with

the

transmitted

frame.

DXMTFCS is overridden when

ADD_FCS and ENP bits are set

in the transmit descriptor.

When the auto padding logic,

which

enabled

the

APAD_XMT bit (CSR4, bit11),

adds padding to a frame, a valid

FCS field is appended to the

frame, regardless of the state of

DXMTFCS.

DXMTFCS

set

and

ADD_FCS is clear for a particular

frame, no FCS will be generated.

If ADD_FCS is set for a particular

frame, the state of DXMTFCS is

ignored and a FCS will be ap-

pended on that frame by the

transmit circuitry. See also the

ADD_FCS bit in the transmit de-

scriptor.

This bit was called DTCR in the

LANCE (Am7990) device.

Read/Write accessible.

LOOP

Loopback

Enable

allows

the

Am79C976 controller to operate

in full-duplex mode for test pur-

poses. The setting of the full-

duplex control bits in BCR9 have

no effect when the device oper-

ates in loopback mode. When

LOOP = 1, loopback is enabled.

In combination with INTL and

MIIILP, various loopback modes

are defined as follows:.

Refer to Loop Back Operation

section for more details.

Read/Write accessible. LOOP is

cle a red

b y

H _ R ESET

S_RESET and is unaffected by

STOP.

DTX

Disable

Transmit

results

Am79C976 controller not access-

ing the Transmit Descriptor Ring

and, therefore, no transmissions

are attempted. DTX = 0, will set

TXON bit (CSR0 bit 4) if STRT

(CSR0 bit 1) is asserted.

Read/Write accessible.

DRX

Disable Receiver results in the

Am79C976 controller not access-

ing the Receive Descriptor Ring

and, therefore, all receive frame

data are ignored. DRX = 0, will

set RXON bit (CSR0 bit 5) if

STRT (CSR0 bit 1) is asserted.

Read/Write accessible.

&65 5HVHUYHG

Bit

Name

Description

31-0

RES

Reserved locations. Written as

zeros and read as undefined.

LOOP

MIIILP

Function

Normal Operation

Internal Loop

External Loop

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