AM79C976 datasheet(153/309 Pages) AMD

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8/01/00

Am79C976

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P R E L I M INARY

INT0: Interrupt0

Offset 038h

INT0 identifies the source or sources of an interrupt.

With the exception of INTR, all bits in this register are

“write 1 to clear” so that the CPU can clear the interrupt

condition by reading the register and then writing back

the same data that it read. Writing a 0 to a bit in this reg-

ister has no effect.

All bits in this register are cleared to 0 by H_RESET. In

addition, TINT, TXDNINT, TXSTRTINT, and RINT are

cleared when the RUN bit in CMD0 is cleared.

Table 59. INT0: Interrupt0 Register

Bit

Name

Description

INTR

Interrupt Summary. This bit indicates that one or more of the other interrupt bits in this register are

set and the associated enable bit or bits in INTEN0 are also set. If INTREN in CMD0 is set to 1 and

INTR is set, INTA will be active. When INTR is set by SINT, INTA will be active independent of the

state of INEA.

INTR is read only. INTR is cleared by clearing all of the active individual interrupt bits that have not

been masked out.

31-28

RES

Reserved locations. Written as zeros and read as undefined.

LCINT

Link Change Interrupt. This bit is set when the Port Manager detects a change in the link status of

the external PHY.

APINT5

Auto-Poll Interrupt from Register 5. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 5.

APINT4

Auto-Poll Interrupt from Register 4. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 4.

APINT3

Auto-Poll Interrupt from Register 3. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 3.

RES

Reserved locations. Written as zeros and read as undefined.

APINT2

Auto-Poll Interrupt from Register 2. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 2.

APINT1

Auto-Poll Interrupt from Register 1. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 1.

APINT0

Auto-Poll Interrupt from Register 0. This bit is set when the Auto-Poll State Machine has detected

a change in the external PHY register whose address is stored in Auto-Poll Register 0.

MIIPDTINT

MII PHY Detect Transition Interrupt. The MII PHY Detect Transition Interrupt is set by the

Am79C976 controller whenever the MIIPD bit in STAT0 transitions from 0 to 1 or vice versa.

This bit is an alias of CSR7, bit 1.

MCCIINT

MII Management Command Complete Internal Interrupt. The MII Management Command

Complete Interrupt is set by the Am79C976 controller when a read or write operation on the MII

management port is complete from an internal operation. Examples of internal operations are Auto-

Poll or Network Port Manager generated MII management frames.

This bit is an alias of CSR7, bit 3.

MCCINT

MII Management Command Complete Interrupt. The MII Management Command Complete

Interrupt is set by the Am79C976 controller when a read or write operation to the MII Data Port

(PHY Access Register) is complete.

This bit is an alias of CSR7, bit 5.

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