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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C976 датащи(PDF) 152 Page - Advanced Micro Devices |
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AM79C976 датащи(HTML) 152 Page - Advanced Micro Devices |
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152 / 309 page  152 Am79C976 8/01/00 P R E L I M INARY ,)6 ,QWHU)UDPH 6SDFLQJ3DUW5HJLVWHU Offset 18Ch The contents of this register are set to 3ch when the RST pin is asserted, before the serial EEPROM is read, and after a serial EEPROM read error. Table 58. IFS1: Inter-Frame Spacing Part 1 Register 16 FCCMD Flow Control Command. In full-duplex mode this bit allows the host CPU to cause a Pause Frame to be sent by issuing a single command. In half-duplex mode, setting this bit puts the device into back-pressure mode, which has the effect of forcing the remote transmitter to delay transmissions while the local system is freeing up congested resources. If the device is operating in full-duplex mode and the value of the FIXP bit is 1, when FCCMD is changed from 0 to 1, a Pause Frame is sent with its Request_operand field copied from the PAUSE_LEN field of this register. After the Pause Frame is sent, the FCCMD bit is automatically reset to 0. If the device is operating in full-duplex mode and the value of the FIXP bit is 0, when FCCMD is changed from 0 to 1, a Pause Frame is sent with its Request_operand field filled with all 1s, and the FCCMD bit is not automatically reset to 0. When FCCMD is changed from 1 to 0, a Pause Frame is sent with its Request_operand field filled with all 0s. If the device is operating in half-duplex mode, setting FCCMD to 1 puts the MAC into back-pressure mode. In back-pressure mode, whenever the MAC detects receiver activity, it transmits a series of alternating 1s and 0s to force a collision. If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the register will not be altered. 15-0 PAUSE_LEN Pause Length. The contents of this field are copied into the Request_operand fields of MAC Control Pause Frames that are transmitted while the FIXP bit in this register is set to 1. Bit Name Description Bit Name Description 7-0 IFS1 InterFrameSpacingPart1. Changing IFS1 allows the user to program the value of the InterFrame- SpacePart1 timing. The Am79C976 controller sets the default value at 60 bit times (3ch). See the subsection on Medium Allocation in the section Media Access Management for more details. The equation for setting IFS1 when IPG 96 bit times is: IFS1 = IPG - 36 bit times IPG should be programmed to the nearest nibble. The two least significant bits are ignored. For example, programming IPG to 63h has the same effect as programming it to 60h. This register is an alias for CSR125, bits [7:0]. |
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