AM79C976 datasheet(156/309 Pages) AMD

156 / 309 page

156

Am79C976

8/01/00

P R E L I M INARY

MPINTEN

Magic Packet Interrupt Enable. When this bit is set, the INTR bit will be set when the MPINT bit in

INT0 is set.

This bit is an alias of CSR5, bit 3.

SINTEN

System Interrupt Enable. When this bit is set, the INTR bit will be set when the SINT bit in INT0 is

set.

This bit is an alias of CSR5, bit 10.

11-9

RES

Reserved locations. Written as zeros and read as undefined.

8TINTEN

Transmit Interrupt Enable. When this bit is set, the INTR bit will be set when the TINT bit in INT0 is

set.

This bit is an alias of CSR3, bit 9 with reversed polarity. (When TINTM in CSR3 is set, the transmit

interrupt is disabled.)

Previous devices in the PCnet family enable receive and transmit interrupts following reset. The

Am79C976 controller disables these interrupts following H_RESET (but not S_RESET). For

compatibility with legacy software, the Am79C976 controller will set RINTEN and TINTEN following

S_RESET. If, in addition, the user programs the EEPROM to load ones into RINTEN and TINTEN,

these interrupts will also be enabled after H_RESET. This matches the behavior of the previous

PCnet devices.

7VAL1

Value bit for byte 1. The value of this bit is written to any bits in the INTEN0 register that correspond

to bits in the INTEN0[6:0] bit map field that are set to 1.

TXDNINTEN

Transmission Done Interrupt Enable. When this bit is set, the INTR bit will be set when the

TXDNINT bit in INT0 is set.

This bit is an alias of CSR5, bit 12.

TXSTRTINTEN

Transmit Start Interrupt Enable. When this bit is set, the INTR bit will be set when the TXSTRTINT

bit in INT0 is set.

This bit is an alias of CSR4, bit 2.

4STINTEN

Software Timer Interrupt Enable. When this bit is set, the INTR bit will be set when the STINT bit

in INT0 is set.

This bit is an alias of CSR7, bit 10.

3-1

RES

Reserved locations. Written as zeros and read as undefined.

0RINTEN

Receive Interrupt Enable. When this bit is set, the INTR bit will be set when the RINT bit in INT0 is

set.

This bit is an alias of CSR3, bit 10 with reversed polarity. (When RINTM in CSR3 is set, the receive

interrupt is disabled.)

Previous devices in the PCnet family enable receive and transmit interrupts following reset. The

Am79C976 controller disables these interrupts following H_RESET (but not S_RESET). For

compatibility with legacy software, the Am79C976 controller will set RINTEN and TINTEN following

S_RESET. If, in addition, the user programs the EEPROM to load ones into RINTEN and TINTEN,

these interrupts will also be enabled after H_RESET. This matches the behavior of the previous

PCnet devices.

Bit

Name

Description

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