AM79C976 datasheet(151/309 Pages) AMD

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Am79C976

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P R E L I M INARY

FLOW: Flow Control Register

Offset 0C8h

FLOW is a command-style register. All bits in this reg-

ister are cleared to 0 when the RST pin is asserted, be-

fore the serial EEPROM is read, and after a serial

EEPROM read error.

Table 57.

FLOW: Flow Control Register

Bit

Name

Description

31-24

RES

Reserved locations. Written as zeros and read as undefined.

VAL2

Value bit for byte 2. The value of this bit is written to any bits in the FLOW register that correspond

to bits in the FLOW[22:16] bit map field that are set to 1.

22-21

RES

Reserved locations. Written as zeros and read as undefined.

FPA

Force Pause Ability. When this bit is set, Pause Ability is enabled regardless of the Pause Ability

state of the external PHY’s link partner. When Pause Ability is enabled, the receipt of a MAC

Control Pause Frame causes the device to stop transmitting for a time period that is determined by

the contents of the Pause Frame.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the

NPA

Negotiate Pause Ability. When this bit is set and the Force Pause Ability bit is not set, Pause Ability

is enabled only if the auto-negotiation process determines that the external PHY’s link partner

supports IEEE 802.3 flow control. When Pause Ability is enabled, the receipt of a MAC Control

Pause Frame causes the device to stop transmitting for a time period that is determined by the

contents of the Pause Frame.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the

FIXP

Fixed Length Pause. When this bit is set to 1, all MAC Control Pause Frames transmitted from the

device will contain a Request_operand field that is copied from the PAUSE_LEN field of this

When this bit is cleared to 0, a Pause Frame with its Request_operand field set to 0FFFFh will be

sent when the FCCMD bit in this register is changed from 0 to 1 or when the signal on the FC pin

changes from 0 to 1 while the FCPEN bit has the value 1. Also a Pause Frame with its

Request_operand field set to 0000h will be sent when the FCCMD bit in this register is changed

from 1 to 0 or when the signal on the FC pin changes from 1 to 0 while the FCPEN bit has the value

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the

FCPEN

Flow Control Pin Enable. When the value of this bit is 1, MAC Control Pause frames will be

transmitted or half-duplex back pressure will be applied when the FC pin is asserted. When the

value of this bit is 0, the state of the FC pin is ignored.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the

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