AM79C976 datasheet(137/309 Pages) AMD

137 / 309 page

8/01/00

Am79C976

137

P R E L I M INARY

RXFRTGEN

Receive Frame Tag Enable. When this bit is set, frame tag data that is shifted in through the

External Address Detection Interface (EADI) while a frame is being received will be copied to the

receive descriptor.

MPPLBA

Magic Packet Physical Logical Broadcast Accept. If MPPLBA is at its default value of 0, the

Am79C976 controller will only detect a Magic Packet frame if the destination address of the

packet matches the content of the physical address register (PADR). If MPPLBA is set to 1, the

destination address of the Magic Packet frame can be unicast, multicast, or broadcast. Note that

the setting of MPPLBA only affects the address detection of the Magic Packet frame. The Magic

Packet frame’s data sequence must be made up of 16 consecutive physical addresses

(PADR[47:0]) regardless of what kind of destination address it has. This bit is OR’ed with

EMPPLBA bit (CSR116, bit 6).

This bit is an alias of CSR5, bit 5.

MPPEN_EE

Magic Packet Pin Enable. When either this bit or the MPPEN_SW bit in CMD7 is set, the device

enters the Magic Packet mode when the PG input goes LOW. This bit has the same function as

MPPEN_SW except that H_RESET clears MPPEN_EE to 0, while H_RESET has no effect on

MPPEN_SW.

This bit is an alias of CSR116, bit 4.

7VAL0

Value bit for byte 0. The value of this bit is written to any bits in the CMD3 register that correspond

to bits in the CMD3[6:0] bit map field that are set to 1.

MPEN_EE

Magic Packet Enable. When either this bit or the MPEN_SW bit in CMD7 is set, the device enters

the Magic Packet mode. This bit has the same function as MPEN_SW except that H_RESET

clears MPEN_EE to 0, while H_RESET has no effect on MPEN_SW.

LCMODE_EE

Link Change Wake-up Mode. When either this bit or the LCMODE_SW bit in CMD7 is set to 1,

the LCDET bit gets set when the MII auto polling logic detects a Link Change. This bit has the

same function as LCMODE_SW except that H_RESET clears LCMODE_EE to 0, while

H_RESET has no effect on LCMODE_SW.

This bit is an alias of CSR116, bit 8.

4PME_EN_OVR

PME_EN Overwrite. When this bit is set and the MPMAT or LCDET bit is set, the PME pin will

always be asserted regardless of the state of PME_EN bit.

This bit is an alias of CSR116, bit 10.

RWU_DRIVER

RWU Driver Type. If this bit is set to 1, RWU is a totem pole driver; otherwise, RWU is an open

drain output.

This bit is an alias of CSR116, bit 3.

2RWU_GATE

RWU Gate Control. If this bit is set, RWU is forced to the high Impedance State when PG is LOW,

regardless of the state of the MPMAT and LCDET bits.

This bit is an alias of CSR116, bit 2.

1RWU_POL

RWU Pin Polarity. If RWU_POL is set to 1, the RWU pin is normally HIGH and asserts LOW;

otherwise, RWU is normally LOW and asserts HIGH.

This bit is an alias of CSR116, bit 1.

0RST_POL

PHY_RST Pin Polarity. If the PHY_POL is set to 1, the PHY_RST pin is active LOW; otherwise,

PHY_RST is active HIGH.

This bit is an alias of CSR116, bit 0.

Bit

Name

Description

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