AM79C976 datasheet(138/309 Pages) AMD

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138

Am79C976

8/01/00

P R E L I M INARY

CMD7: Command7

Offset 064h

CMD7 is a command-style register. All bits in this reg-

ister are cleared to 0 when power is first applied to the

device (power-on reset). The contents of this register

are not affected by the state of the RST pin. The con-

tents of this register can not be loaded from the

EEPROM. Therefore, the contents of this register are

not disturbed when PCI bus power is removed and re-

applied.

Table 45. CMD7: Command7 Register

Bit

Name

Description

31-8

RES

Reserved locations. Written as zeros and read as undefined.

7VAL0

Value bit for byte 0. The value of this bit is written to any bits in the CMD7 register that correspond

to bits in the CMD7[6:0] bit map field that are set to 1.

6-4

RES

Reserved locations. Written as zeros and read as undefined.

3PMAT_MODE

Pattern Match Mode. Writing a 1 to this bit will enable Pattern Match Mode and should only be done

after the Pattern Match RAM has been programmed.

Pattern Match Mode is enabled when either this bit or BCR45, bit 7 is set.

MPPEN_SW

Magic Packet Pin Enable. When either this bit or the MPPEN_EE bit in CMD3 is set, the device

enters the Magic Packet mode when the PG input goes LOW. This bit has the same function as

MPPEN_EE except that H_RESET clears MPPEN_EE to 0, while H_RESET has no effect on

MPPEN_SW.

MPEN_SW

Magic Packet Software Mode Enable. The Am79C976 controller enters the Magic Packet mode

when this bit is set to 1. This bit has the same function as MPEN_EE except that H_RESET clears

MPEN_EE to 0, while H_RESET has no effect on MPEN_SW.

LCMODE_SW

Link Change Wake-up Mode. When either this bit or the LCMODE_EE bit in CMD3 is set to 1, the

LCDET bit gets set when the MII auto polling logic detects a Link Change. This bit has the same

function as LCMODE_EE except that H_RESET clears LCMODE_EE to 0, while H_RESET has

no effect on LCMODE_SW.

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