AM79C976 datasheet(135/309 Pages) AMD

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8/01/00

Am79C976

135

P R E L I M INARY

CMD3: Command3

Offset 054h

CMD3 is a command-style register. All bits in this reg-

ister are cleared to 0 when the RST pin is asserted, be-

fore the serial EEPROM is read, and after a serial

EEPROM read error.

Table 44. CMD3: Command3 Register

Bit

Name

Description

VAL3

Value bit for byte 3. The value of this bit is written to any bits in the CMD3 register that correspond

to bits in the CMD3[30:24] bit map field that are set to 1.

PREFETCH_DIS

Disable Prefetchability. This bit, which can be loaded from EEPROM, is the inverse of the value

reported in the PREFETCH bit in the PCI Memory-Mapped I/O Base Address Register, which is

read-only.

Setting PREFETCH_DIS to 1 indicates that the memory space claimed by this device can not be

prefetched.

Because of the side effects of reading the Reset Register at offset 14h or 18h (depending on the

state of DWIO (CMD2, bit 28)), locations at offsets less than 20h cannot be prefetched. The

Am79C976 device will disconnect any attempted burst transfer at offsets less than 20h.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL3 bit. If a logical 0 is written to this bit position, the corresponding bit in the

DIS_READ_WAIT

Disable Read Wait. When this bit is set to 1, the controller will not insert IRDY wait states in burst

read transfers.

DIS_WRITE_WAIT

Disable Write Wait. When this bit is set to 1, the controller will not insert IRDY wait states in burst

write transfers.

DISABLE_MWI

Disable MWI. When this bit is set to 1, the controller will not generate MWI PCI bus commands.

RST_PHY

Reset PHY. When this bit is set to 1, the controller will assert the PHY_RST signal. The signal

will remain asserted for as long as this bit remains set.

INIT_MIB

Initialize Management Information Base Counters. Setting this bit will cause all of the MIB

counters to be reset to 0. Resetting these counters takes about 55 ERCLK cycles. This bit is

cleared automatically after the counters have all been reset to 0. This bit must not be set to 1 by

the EEPROM logic.

If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with

the contents of the VAL3 bit. If a logical 0 is written to this bit position, the corresponding bit in the

APEP

MII Auto-Poll External PHY (APEP) When set to 1, the Am79C976 controller will poll the MII

status register in the external PHY. This feature allows the software driver or upper layers to see

any changes in the status of the external PHY. An interrupt, when enabled, is generated when

the contents of the new status is different from the previous status.

This bit is an alias of BCR32, bit 11.

VAL2

Value bit for byte 2. The value of this bit is written to any bits in the CMD3 register that correspond

to bits in the CMD3[22:16] bit map field that are set to 1.

RES

Reserved. Written as 1 and read as undefined.

JUMBO

Accept Jumbo Frames. This bit affects the way the MIB counters count long frames. If JUMBO is

0, only frames that are between 64 and 1518 bytes (or 1522 bytes if VLAN is set to 1) are counted

as valid frames. When JUMBO is 1, any frame longer than 63 bytes with a valid FCS field is

counted as a valid frame.

VSIZE

VLAN Frame Size. This bit determines the maximum frame size used for determining when to

increment the XmtPkts1024to1518Octets, XmtExcessiveDefer, RcvPkts1024to1518Octets, and

RcvOversizePkts MIB counters and when to assert the Excessive Deferral Interrupt.

When this bit is set to 1 the maximum frame size is 1522 bytes. When it is cleared to 0, the

maximum frame size is 1518 bytes.

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